Abstract: A wafer level packaging procedure provides a wafer having a pad mounting surface with bonding pads on the pad mounting surface. An insulative layer is formed with conductor formation holes exposing the bonding pads. Conductors are formed in the respective conductor formation holes. A photoresist protective layer is formed on the pad mounting surface and then holes are formed in the photoresist protective layer for exposing parts of the respective conductors. Conductive bumps are formed in the holes in the photoresist protective layer in electric connection to the respective conductors.

Abstract: A semiconductor package comprising a die paddle defining multiple corners and opposed first and second surfaces. At least one set of leads extends at least partially about the die paddle in spaced relation thereto. Each of the leads has opposed first and second surfaces. Attached to and extending from one of the corners of the die paddle is at least one tie bar which itself has opposed first and second surfaces and at least one aperture disposed therein and extending between the first and second surfaces thereof. Attached to the first surface of the die paddle is a semiconductor die which is electrically connected to at least one of the leads. A package body at least partially covers the die paddle, the leads, the tie bar and the semiconductor die such that the second surfaces of the leads are exposed in and substantially flush with a common exterior surface of the package body, and a portion of the package body extends through the aperture of the tie bar.

Abstract: An enhancement mode field effect transistor whose operation threshold value varies greatly according to the substrate voltage. This field effect transistor is implemented by substituting the gate electrode of a depression mode field effect transistor for a gate electrode of the conductivity type opposite to that of a channel formation region, or a midgap gate electrode. In a preferred embodiment of the present invention, this field effect transistor is provided between a CMOS structure logic gate and a ground line. As a result, the leak current when the field effect transistor is not operating can be diminished without reducing the operational speed of the logic gate.

Abstract: A semiconductor package with build-up layers formed on a chip and a fabrication method of the semiconductor package are provided. A chip with a plurality of conductive bumps formed on bond pads thereof is received within a cavity of a carrier, and a dielectric layer encapsulates the conductive bumps whose ends are exposed. A plurality of conductive traces are formed on the dielectric layer and electrically connected to the ends of the conductive bumps. A solder mask layer is applied over the conductive traces and formed with openings via which predetermined portions of the conductive traces are exposed and bonded to a plurality of solder balls. Thereby, positions of the bond pads are easily recognized and distinguished by the exposed ends of the conductive bumps, making the conductive traces capable of being well electrically connected through the conductive bumps to the bond pads to improve yield of the fabricated packages.

Abstract: On an insulating substrate, a first insulating buffer layer, a heat accumulating-light shielding layer having at least a silicon layer on the surface thereof, a second insulating buffer layer and a first silicon layer are laminated in the order recited from the bottom. The lamination structure of the heat accumulating-light shielding layer, second buffer layer and first silicon layer is patterned. A laser beam is applied the patterned first silicon layer to melt and crystallize the first silicon layer. A thin film transistor is formed by using the crystallized first silicon layer. A polysilicon thin film transistor of high performance and small leak current to be caused by light as well as a display device using such thin film transistors is provided.

Abstract: A method of driving a dual-gated MOSFET having a Miller capacitance between the MOSFET gate and drain includes preparing the MOSFET to switch from a blocking mode to a conduction mode by applying to the MOSFET shielding gate a first voltage signal having a first voltage level. The first voltage level is selected to charge the Miller capacitance and thereby reduce switching losses. A second voltage signal is applied to the switching gate to switch the MOSFET from the blocking to the conduction mode. The first voltage signal is then changed to a level selected to reduce the conduction mode drain-to-source resistance and thereby reduce conduction losses. The first voltage signal is returned to the first voltage level to prepare the MOSFET for being switched from the conduction mode to the blocking mode.

Abstract: In a circuit to drive driven elements such, as electro-optical elements, an electro-optical device has an element layer, a wire-forming layer, and an electronic component layer in order to suppress variation in characteristics of active elements. The element layer has a plurality of organic EL elements, each of which is arranged in a different position in a plane. The electronic component layer has pixel-driving IC chips. The respective pixel-driving IC chips include a plurality of pixel circuits, each of which drives each organic EL element corresponding to the pixel circuit. The wire-forming layer is positioned between the element layer and the electronic component layer. The wire-forming layer has wires to connect the respective pixel circuits included in the pixel-driving IC chips with the organic EL elements corresponding to the pixel circuits.

Abstract: An intermediate product for an integrated circuit is disclosed. The intermediate product comprises a first portion of a conductive layer, preferably a layer of noble metal, which will form an upper electrode of a capacitor or a patterned wiring. The intermediate product also comprises an adjacent second portion of the conductive layer, the second portion being a removable silicide of the conductive layer.

Abstract: A semiconductor device includes a substrate, a plurality of bonding fingers formed on the surface of the substrate, and a semiconductor element arranged above the surface of the substrate and having a plurality of connection pads on a surface opposite to a surface facing the substrate. The plurality of connection pads have a connection pad group aligned in the vicinity of a side of the semiconductor element along the same. The plurality of bonding fingers have a bonding finger arranged outside sides adjacent to sides of the semiconductor element along which the connection pad group is arranged. The connection pad group has the connection pad electrically connected to the bonding finger by wire bonding. Therefore, a semiconductor device attaining improved degree of freedom in routing without lowering quality and efficient reduction in its outer dimension is obtained.

Abstract: A method for increasing carrier concentration in a semiconductor includes providing a group III nitride semiconductor device, determining a wavelength that increases carrier concentration in the semiconductor device, and directing at least one infrared light source, at the determined wavelength, into a semiconductor device excitation band.

Abstract: A semiconductor device (1) of the present invention includes a semiconductor element (103) including electrode parts (104), and a wiring substrate (108) including an insulation layer (101), electrode-part-connection electrodes (102) provided in the insulation layer (101), and external electrodes (107) that is provided in the insulation layer (101) and that is connected electrically with the electrode-part-connection electrodes (102), in which the electrode parts (104) and the electrode-part-connection electrodes (102) are connected electrically with each other. The insulation layer (101) has an elastic modulus measured according to JIS K6911 of not less than 0.1 GP a and not more than 5 GPa, and the electrodes (104) and the electrode-part-connection electrodes (102) are connected by metal joint.

Abstract: A bump is formed on a bonding pad provided on a substrate. A passivation film covering a bonding pad provided on a semiconductor chip is provided with two apertures in which bumps are formed. The bump provided on the substrate advances and enters into a clearance between these bumps provided on the semiconductor chip when the semiconductor chip is packaged with the substrate.

Abstract: Hexachlorodisilane (Si2Cl6) is used as a Si raw material for forming a silicon nitride film that can be widely different in the etching rate from a silicon oxide film. The silicon nitride film is formed by an LPCVD method.

Abstract: EMI radiation in an integrated circuit device package (10) is reduced or eliminated by the introduction of a magnetic material into the encapsulating medium (14). The permeance of the magnetic encapsulating medium (14) affects the inherent series inductance of the lead frame conductors (16) to thereby reduce electromagnetic interference. Ferrite microbeads (30) are formed around the lead frame conductors (16) to contain the magnetic flux (32) generated by an electrical current signal and to attenuate the effects of mutual inductance.

Abstract: A method of manufacturing a semiconductor device in which a trench groove is formed in a first conductivity type semiconductor layer, and a second conductivity type semiconductor layer is epitaxially grown so as to bury the trench groove. The second conductivity type semiconductor layer is then removed until a surface of the first conductivity type semiconductor layer is exposed. The first conductivity type semiconductor layer is epitaxially grown on the first conductivity type semiconductor layer and the second conductivity type semiconductor layer such that the thickness of the first conductivity type semiconductor layer increases by a length which is substantially the same as a depth of the trench groove.

Abstract: Object of the Invention To obtain thin film transistors with controlled characteristics on a substrate. Means A semiconductor film formed on a substrate is crystallized by continuously oscillating type laser. The scanning direction of the continuously oscillating type laser and the crystallization direction are coincident with each other. Adjustment of the crystallization direction and the charge transferring direction of the thin film transistors makes control of the characteristics of the thin film transistors possible. With respect to the laser treatment device for crystallizing the semiconductor film, the beam shape of laser oscillated from the continuously oscillating type laser device is made to be elliptical by a cylindrical lens and said cylindrical lens is made rotatable and said laser beam is scanned on said substrate by a galvanomirror and said laser beam can be focused upon said substrate by f-? lens.

Abstract: When connecting a semiconductor device such as an IC chip with a circuit board by the flip-chip method, a semiconductor device is provided without forming bumps thereon, which enables highly reliable and low cost connection between the IC chip and circuit board while ensuring suppressing short-circuiting, lowering connection costs, suppressing stress concentrations at the joints and reducing damage of the IC chip or circuit board. The bumpless semiconductor device is provided with electrode pads 2 on the surface thereof and with a passivation film 3 at the periphery of the electrode pads 2, and conductive particles 4 are metallically bonded to the electric pads 2. Composite particles in which a metallic plating layer is formed at the surface of resin particles are employed as the conductive particles 4.

Abstract: A technique for fabricating a patterned resistor on a substrate produces a patterned resistor (101, 801, 1001, 1324, 1374) including two conductive end terminations (110, 810, 1010) on the substrate, a pattern of first resistive material (120, 815, 1015) having a first width (125) and a first sheet resistance, and a pattern of second resistive material (205, 820, 1020) having a second width (210) and a second sheet resistance that at least partially overlies the pattern of first resistive material. One of the first and second sheet resistances is a low sheet resistance and the other of the first and second resistances is a high sheet resistance. A ratio of the high sheet resistance to the low sheet resistance is at least ten to one. The pattern having the higher sheet resistance is substantially wider than the pattern having the low sheet resistance. The patterned resistor can be precision trimmed 1225.

Abstract: A method for forming a contact to a semiconductor fin which can be carried out by first providing a semiconductor fin that has a top surface, two sidewall surfaces and at least one end surface; forming an etch stop layer overlying the fin; forming a passivation layer overlying the etch stop layer; forming a contact hole in the passivation layer exposing the etch stop layer; removing the etch stop layer in the contact hole; and filling the contact hole with an electrically conductive material.

Abstract: The invention includes a DRAM array having a structure therein which includes a first material separated from a second material by an intervening insulative material. The first material is doped to at least 1×1017 atoms/cm3 with n-type and p-type dopant. The invention also includes a semiconductor construction in which a doped material is over a segment of a substrate. The doped material has a first type majority dopant therein, and is electrically connected with an electrical ground. A pair of conductively-doped diffusion regions are adjacent the segment, and spaced from one another by at least a portion of the segment. The conductively-doped diffusion regions have a second type majority dopant therein. The invention also encompasses methods of forming semiconductor constructions.