Abstract: A method of fabricating a dual bit dielectric memory cell structure on a silicon substrate includes implanting buried bit lines within the substrate and fabricating a layered island on the surface of the substrate between the buried bit lines. The island has a perimeter defining a gate region, and comprises a tunnel dielectric layer on the surface of the silicon on insulator wafer, an isolation barrier dielectric layer on the surface of the tunnel dielectric layer, a top dielectric layer on the surface of the isolation barrier dielectric layer, and a polysilicon gate on the surface of the top dielectric layer. A portion of the isolation barrier dielectric layer is removed to form an undercut region within the gate region and a charge trapping material is deposited within the undercut region.

Abstract: Exposure positions of exposure fields of semiconductor wafers are subsequently corrected individually in order to compensate for processes affecting the locational position of alignment marks and/or oblique measurement structures. Measurement structures are formed preferably in the frame region of product wafers comprising electrical circuits to be formed and their locational positions before and after the effect of the process that has an effect are compared individually for purpose of determining the positional displacement for each relevant exposure field. From this there is determined either directly a “shot”-fine correction value for the individual exposure or at least one nonlinear function for the correction in dependence on the position of the measurement structures on the wafer. The corrections are applied to the exposure fields after alignment to the alignment marks overformed by the process in dependence on their position on the wafer.

Abstract: The present invention is to provide a double-sided thermally enhanced IC chip package which includes a chip being received in an opening of a substrate and electrically connected to a conductive circuit pattern on a top surface of the substrate through bonding wires. A thermally and electrically conductive planar member is attached to an inactive side of the chip through a thermally and electrically conductive adhesive layer. A portion of an active side of the chip to which the bonding wires are connected is encapsulated by a dielectric encapsulant, and the other portion of the active side of the chip is covered by a thermally and electrically conductive encapsulant. Thus, heat generated by the chip can be efficiently dissipated through the planar member and the thermally and electrically conductive encapsulant. The present invention also discloses a stacked chip package with double-sided heat dissipation capability.

Abstract: A semiconductor device includes a first-conductivity-type semiconductor layer which includes a cell region portion and a junction terminating region portion. The junction terminating region portion is a region portion which is positioned in an outer periphery of the cell region portion to maintain a breakdown voltage by extending a depletion layer to attenuate an electric field.

Abstract: Light emitting LEDs devices comprised of LED chips that emit light at a first wavelength, and a thin film layer over the LED chip that changes the color of the emitted light. For example, a blue LED chip can be used to produce white light. The thin film layer beneficially consists of a florescent material, such as a phosphor, and/or includes tin. The thin film layer is beneficially deposited using chemical vapor deposition.

Abstract: An integrated circuit includes a heterojunction thyristor device having an anode terminal, a cathode terminal, a first injector terminal operably coupled to a first quantum well channel disposed between the anode terminal and the cathode terminal, and a second injector terminal operably coupled to a second quantum well channel disposed between the anode terminal and the cathode terminal. Bias elements operate the heterojunction thyristor device in a mode that provides substantially linear voltage gain for electrical signals supplied to at least one of the first and second injector terminals for output to at least one output node.

Abstract: A method for increasing carrier concentration in a semiconductor includes providing a group III nitride semiconductor device, determining a wavelength that increases carrier concentration in the semiconductor device, and directing at least one infrared light source, at the determined wavelength, into a semiconductor device excitation band.

Abstract: A III-nitride light emitting device includes an n-type layer, a p-type layer, and an active region capable of emitting light between the p-type layer and the n-type layer. The active region includes at least one additional p-type layer. The p-type layer in the active region may be a quantum well layer or a barrier layer. In some embodiments, both the quantum well layers and the barrier layers in the active region are p-type. In some embodiments, the p-type layer in the active region has an average dislocation density less than about 5×108 cm−2.

Abstract: A method for producing semiconductor laser components in which, a number of chip mounting areas are formed on a cooling element having an electrically insulating carrier that is in the form of a plate. A number of semiconductor laser chips are then fit to the cooling element, with one semiconductor laser chip being arranged on each chip mounting area. Finally, the cooling element, with the semiconductor bodies fit on it, is subdivided into a number of semiconductor laser components.

Abstract: Disclosed is a method of forming a fine pattern in a semiconductor device using a photolithography process, which comprises: coating a photoresist layer for an I-line and a positive type ArF photoresist layer on a semiconductor substrate that includes a conductive layer; performing exposure and a first baking process on the resultant substrate by using an etch-mask of a desired pattern to produce alcohol radicals (OH−) or carboxyl acid (COOH) in the positive type ArF photoresist layer, in which a silylation reaction can be produced; removing the etch-mask; performing a development process to the resultant structure to form a first photoresist pattern; performing exposure and a second baking process on the substrate that includes the first photoresist pattern; performing a silylation process to the substrate to which the second baking process has been performed, by using an HMDS to form a silicon oxide layer on the surface of the first photoresist pattern through reaction between the alcohol radicals (OH

Abstract: An optical semiconductor device of the present invention is equipped with a photo detect element 10 comprising a photo detect part 7 provided with two photodiodes having two photodiodes having peak wavelength sensitivity in a visible light region and an infrared region, respectively and an amplifying operation processing circuit 8 for amplifying and processing outputs of the photodiodes, and characterized in that substrate resistivity R is as follows: 1≦R≦3(&OHgr;cm)

Abstract: A ball grid array semiconductor packaging technology is provided, which is characterized in that openings of a solder mask are formed on a given edge of a die attachment area, and entire or partial width of each opening is disposed outside the die attachment area. Accordingly, air within the opening of the solder mask is sufficiently eliminated during die bonding process, so as to prevent void formation as adhesive is filled into the opening. Therefore, in the follow-up steps, high temperature in reflowing process will not cause popcorn as in the prior-art, so as to remain good quality of the semiconductor package.

Abstract: An oxide layer on an indium phosphide semiconductor substrate is doped with silicon. This enables epitaxial layers to be deposited upon the substrate in a conventional manner, including mesa etching and overgrowth, to form a semiconductor structure. The doped oxide layer is thought to reduce diffusion of phosphorus out of the substrate and thus to reduce the zinc levels in the active region of the structure. Additionally, or as an alternative, after mesa etching oxide can be formed on the mesa sides and then doped with silicon. Conventional blocking layers can then be formed over the doped oxide, reducing the diffusion of zinc from the blocking layers into the rest of the structure.

Abstract: A semiconductor package assembly 10 has an intervening package (12) that may be connected to a first package (14) from a first substrate (20) on a first side of the package (12) and to a second package (13) from a second substrate (53) on a second, opposing side of the package (12). Electrical contact to a semiconductor die (32) is made from the first side by wire bonding to wire bond posts (26) and by balls (46, 48) from the second side. Electrical contact from one side of the intervening package (12) to the other may be made by bypassing the die. Electrical contact on either side of the intervening package may be made both within and outside the footprint of the semiconductor die (32).

Abstract: A semiconductor package comprises a board, a plurality of solder bump pads, a plurality of board pads, a plurality of distribution patterns, a plurality of contact pads, at least one chip, a plurality of bonding wire, an encapsulation part and a plurality of solder bumps. In order to reduce the height of the loop of the bonding wires for connecting the bonding pad on the semiconductor chip to the board pads on the board, the ends of the bonding wires are connected to the bonding pads and board pads respectively by wedge bonding. Thus, a very thin package can be obtained. In addition, a thin package stack can be obtained by stacking the very thin packages.

Abstract: In a semiconductor device having the upmost wiring layer comprised of aluminum and the wiring layer immediately below it comprised of copper, the upmost wiring layer is made thicker than the wiring layer immediately below it so that the upmost wiring layer is lower in sheet resistance than the wiring layer immediately below it. Multiple ring power lines VR and pads PD are formed of the upmost wiring layer, and the ring power lines VR and the pads PD are connected respectively through power lines VLB1 of the upmost wiring layer. Consequently, the voltage drop on the power feed path from the pads PD to the ring power lines VR can be reduced and the power conduction from the pads PD to the ring power lines VR can be stabilized.

Abstract: Plasma charging devices and methods are disclosed for detecting plasma charging during semiconductor wafer processing. Charging monitors are disclosed having ferroelectric capacitance elements which can be preprogrammed prior to processing steps of interest, and then subsequently measured afterwards, in order to determine whether plasma related charging is a problem in the intervening processing steps.

Abstract: In a manufacturing method in which a source line is provided around a pixel electrode provided on a substrate, an insulating film having open regions that will provide a source and a gate is formed, the source and the drain are formed, and a semiconductor film and a gate are provided on the source and drain, the above constituents are formed substantially under atmospheric pressure. Since manufacture can be accomplished substantially under the atmospheric pressure, no special apparatus, such as a vacuum chamber, is required, permitting a display device to be manufactured at lower cost.

Abstract: A semiconductor device includes a patterned conductive layer on which an initial dielectric film is deposited by a non-etching deposition process. A second dielectric film is then deposited on the initial dielectric film by high-density plasma chemical vapor deposition (HDP CVD). The HDP CVD process etches the second dielectric film as it is being deposited, thereby smoothing the surface of the second dielectric film. The initial dielectric film insulates the patterned conductive layer from the plasma used in the HDP CVD process, so that plasma charge is not conducted to underlying oxide films, such as gate oxide films, and does not cause oxide damage.

Abstract: A semiconductor memory apparatus that stores data by accumulating charges in its capacitor is provided for allowing itself to be operated at a low potential and at a high speed. In the semiconductor memory apparatus, before performing a precharge by a precharging circuit 10 for the next cycle of read and write, a forced step-down circuit 11 previously lowers the potential of the bit line BL charged on the high side to a level within the range of preventing data of positive charges written and stored in a memory cell MC from being disappeared.