Abstract: A method is disclosed for forming high-quality high-crystallinity polycrystalline or monocrystalline thin semiconductor film. The method is capable of forming such a semiconductor film over a large area at low cost. An apparatus for practicing the method is also disclosed. To form a high-crystallinity large-grain polycrystalline film or monocrystalline thin semiconductor film on a substrate, or to produce a semiconductor device including a high-crystallinity large-grain polycrystalline film or monocrystalline thin semiconductor film disposed on a substrate, a low-crystal-quality thin semiconductor film is first formed on the substrate, and then focused-light annealing is performed on the low-crystal-quality thin semiconductor film thereby melting or semi-melting the low-crystal-quality thin semiconductor film.

Abstract: An improved finger structure applied to a packaging stack structure. The packaging stack structure is composed of several layers of chips, each chip is formed several leading wires and several finger sets are connected to the leading wire. Several finger units are formed on a finger set. The shape of these finger units is a strip structure with a bending angle, and the shape of these finger units is along an obverse direction of these leading wires to the finger unit and is changed corresponding to the obverse direction of the finger unit. The present invention can simplify the process and improve the reliability by changing the finger structure and continuously using the obverse bonding process to avoid the striking strength of the reverse bonding process.

Abstract: A color OLED device is described having one or more pixels, at least one pixel comprising: four or more light-emitting elements, each light-emitting element comprising one or more layers of electroluminescent organic material producing a broadband light having a variable frequency-dependent luminous efficacy emission spectrum, and each light-emitting element further comprising a filter for filtering the broadband light and emitting a different color of light; wherein the different colors of light emitted by three of the light-emitting elements specify a first color gamut of the OLED device, and an additional one or more of the light-emitting elements emit at least one additional different color of light and wherein the frequency range of the filter of the additional light emitting element is matched to a portion of the broadband light frequency range having a radiant intensity greater than the radiant intensity of the frequency range of at least one of the filters of the three light-emitting elements specifyi

Abstract: A radiation detector (10) has a base (30), a frame (48), a window (46), and solder layers (50, 52) formed from a solder pre-form (58, 60) to define a vacuum chamber (56). Feedthroughs (18, 40, 44) penetrate the base (30) for electrical connection to internal components. A method for sealing the detector (10) aligns a lower detector assembly (62), the frame (48) the window (46), and the solder pre-forms (58, 60) in a non-sealed relation within a processing chamber (80, 94). High temperature and low pressure is imposed, and the getter (42) is activated by resistive heating imposed by current leads (88). The window (46), frame (48), and lower detector assembly (62) are then pressed together and sealed by the liquefied solder pre-forms (58, 60). The method eliminates the need for a seal port, combines several steps within the processing chamber (80, 94), and eliminates certain prior art cleaning steps.

Abstract: An apparatus including a first substrate comprising a first set of contact points; a second substrate including a second set of contact points coupled to the first substrate through interconnections between a portion of the first set of contact points a portion of the second set of contact points; and a composition disposed between the first substrate and the second substrate including a siloxane-based aromatic diamine.

Abstract: A resistive element controllable to irreversibly decrease its value, including several polysilicon resistors connected in series between two input/output terminals of the resistive lemen; and an assembly of switches, connected to turn the series connection into a parallel association of said resistors between two programming terminals intended to receive a supply voltage.

Abstract: According to one embodiment, a memory structure comprises a substrate having a channel region situated between a source region and a drain region. The memory structure further comprises a gate layer formed over the channel region of the substrate, and a tunable interlayer dielectric formed over the gate layer and the substrate. The tunable interlayer dielectric has a transparent state and an opaque state, and comprises a matrix and electrically or magnetically tunable material situated within the matrix. During the transparent state, UV rays can pass through the tunable interlayer dielectric to the gate layer, e.g., to perform a UV erase operation. During the opaque state, UV rays are prevented from passing through the tunable interlayer dielectric to the gate layer, thereby protecting the gate layer against unwanted charge storage and extrinsic damage that may occur during various processes.

Abstract: A crystalline semiconductor film in which the position and the size of crystal grains are controlled is provided, and a TFT that can operate at high speed is obtained by forming a channel formation region of the TFT from the crystalline semiconductor film. A heat retaining film is formed on an insulating surface, a semiconductor film is formed to cover the heat retaining film, and a reflective film is formed to partially cover the semiconductor film. The reflective films and the semiconductor film are irradiated with a laser beam. The reflective film creates a distribution in effective irradiation intensity of laser beam on the semiconductor film. The distribution, with the heat retaining effect provided by the heat retaining film, generates a temperature gradient in the semiconductor film. Utilizing these, the position where crystal nuclei are to be generated and the direction in which crystal growth should advance can be controlled and crystal grains having a large grain size can be obtained.

Abstract: A sheet guide device having a first sheet guide path and a second sheet guide path intersecting with each other for guiding a sheet and a pivotally movable guide member pivotally movably provided on a common downstream side corner of the first sheet guide path and the second sheet guide path in an intersecting portion between the first sheet guide path and the second sheet guide path, wherein the pivotally movable guide member is pushed and pivotally moved by the leading edge portion of the sheet passing the intersecting portion to thereby guide the sheet.

Abstract: A light-emitting device and method for fabricating the same are revealed. The light-emitting device includes an epitaxial structure, a P-type ohmic contact electrode and an N-type ohmic contact electrode. The epitaxial structure includes a plurality of epitaxial layers capable of emitting light and P-type contact layer. The P-type ohmic contact electrode includes a first nickel layer deposited on the epitaxial structure, a first platinum layer deposited on the first nickel layer, and a first gold layer deposited on the first platinum layer. According to the fabricating method of the light-emitting device, an epitaxial structure is first formed on the surface of a substrate, a P-type ohmic contact electrode is then formed on the epitaxial structure, and an N-type ohmic contact electrode is formed on the other surface of the substrate. Finally, an annealing process is performed at a temperature between 220° C. and 330° C.

Abstract: The present invention is directed to a process for producing a silicon on insulator (SOI) structure having intrinsic gettering, wherein a silicon substrate is subjected to an ideal precipitating wafer heat treatment which enables the substrate, during the heat treatment cycles of essentially any arbitrary electronic device manufacturing process to form an ideal, non-uniform depth distribution of oxygen precipitates, and wherein a dielectric layer is formed beneath the surface of the wafer by implanting oxygen or nitrogen ions, or molecular oxygen, beneath the surface and annealing the wafer. Additionally, the silicon wafer may initially include an epitaxial layer, or an epitaxial layer may be deposited on the substrate during the process of the present invention.

Abstract: The method of protecting micromechanical structures during a wafer fabrication process. A protective layer 402 is deposited to protect the fragile microstructures during a wafer separation process and a post separation cleanup process. Suitable protective layers 402 typically are plastic and tend to deform or delaminate when the wafer is sawn. The deformation of the protective overcoat during the saw process destroys the structures it is intended to protect. To prevent deformation of the protective layer 402, a brittle layer 404 is deposited on the protective layer 402 to hold the protective layer in place during the saw process. Cured photoresist is a suitable protective layer. The photoresist can be applied to the protective layer using standard processes and cured, typically by baking the photoresist. Once the wafer is separated, the brittle layer may be removed. After the debris created during the saw process is removed, the protective overcoat may be removed.

Abstract: Hexachlorodisilane (Si2Cl6) is used as a Si raw material for forming a silicon nitride film that can be widely different in the etching rate from a silicon oxide film. The silicon nitride film is formed by an LPCVD method.

Abstract: The present invention discloses the formation of a hard mask layer in an organic polymer layer by modifying at least locally the chemical composition of a part of said exposed organic low-k polymer. This modification starts from an exposed surface of the polymer and extends into the polymer thereby increasing the chemical resistance of the modified part of the polymer. As a result, this modified part can be used as a hard mask or an etch stop layer for plasma etching.

Abstract: There is disclosed a semiconductor light-emitting element comprising a substrate having a first surface and a second surface, a semiconductor laminate formed on the first surface of the substrate and containing a light-emitting layer and a current diffusion layer having a light-extracting surface. The light-emitting element is provided with a light-extracting surface which is constituted by a finely recessed/projected surface, 90% of which is constructed such that the height of the projected portion thereof having a cone-like configuration is 100 nm or more, and the width of the base of the projected portion is within the range of 10-500 nm.

Abstract: An integrated circuit memory device includes a semiconductor substrate and a first electrically insulating layer that extends on the semiconductor substrate and has a first contact hole extending therethrough. An electrically conductive plug is provided in the first contact hole. A phase-change material layer pattern is provided as a non-volatile storage medium. The phase-change material layer pattern has a bottom surface that is electrically connected to the electrically conductive plug. A second electrically insulating layer is provided on the phase-change material layer pattern. The second electrically insulating layer has a second contact hole therein. This contact hole exposes a portion of an upper surface of the phase-change material layer pattern. To improve data writing efficiency, the area of the exposed portion of the upper surface of the phase-change material layer pattern is less than a maximum cross-sectional area of the electrically conductive plug. A plate electrode is also provided.

Abstract: A flip chip package structure comprising a chip, a substrate, at least a first bump and a plurality of second bumps is provided. The chip has a first bump-positioning region and the substrate has a second bump-positioning region. The substrate has at least a first hole and multiple second holes. The first hole and the second holes are located within the second bump-positioning region. The first hole has a depth greater than that of the second hole. The first bump is set up between the first bump-positioning region of the chip and the second bump-positioning region of the substrate. The first bump is bonded to the substrate through the first holes. The second bumps are set up between the first bump-positioning region of the chip and the second bump-positioning region of the substrate. The second bumps are bonded to the substrate through the second holes. The first bump has a volume greater than the volume of the second bump.

Abstract: Metal structures for ICs and methods for manufacturing the same are described. The metal structures range from small features to large features and are resistant to peeling problems during heat treatments that occur during the manufacturing process. Peeling of the metal structures from the underlying structures or substrates is reduced or prevented. The peeling problems are reduced or prevented by including a capping layer or capping structure over the dielectric layer over the metal structure and then annealing the capping layer or capping structure, thereby enhancing the adhesion of the metal structure to the underlying structure or substrate.

Abstract: A silicon on insulator (SOI) substrate includes a layer of silicon carbide beneath an insulating layer on which semiconductor devices are formed. The silicon carbide layer has a high thermal conductivity and provides beneficial dissipation of thermal energy generated by the devices. The SOI substrate may be formed by a bonding method. SOI MOSFET devices using the SOI substrate are also disclosed.

Abstract: A strained silicon MOSFET employs a high thermal conductivity insulating material in the trench isolations to dissipate thermal energy generated in the MOSFET and to avoid self-heating caused by the poor thermal conductivity of an underlying silicon germanium layer. The high thermal conductivity material is preferably silicon carbide, and the isolations preferably extend through the silicon germanium layer to contact an underlying silicon layer so as to conduct thermal energy from the active region to the silicon layer.