Abstract: A monolithic bidirectional switch formed in an N-type semiconductor substrate, including, in a first area, a first vertical thyristor adjacent to a second vertical thyristor; a triggering area arranged on the front surface side, apart from the first area, including a P-type well in which is formed an N-type region; a first metallization covering the rear surface; a second metallization on the front surface layers of the first and second thyristors; a third gate metallization on said well; on the rear surface side, an additional P-type region and an insulating layer interposed between this additional region and the first metallization, the additional region extending under the triggering area; and a fourth metallization on the region.

Abstract: A semiconductor device which IGBT (Z1) and a control circuit (B1) for driving the IGBT (Z1) are formed on the same semiconductor substrate by using a junction isolation technology, includes an input terminal (P1) for inputting a drive signal of the IGBT (Z1), a Schottky barrier diode (D2) having an anode connected to the input terminal (P1) and a cathode connected to an input terminal (B11) of the control circuit (B1), and a p-channel MOSFET (T1) for shorting both ends of the Schottky barrier diode (D2) when the voltage of the drive signal input to the input terminal (P1) is higher than a predetermined voltage, thereby latch-up of the parasitic element is prevented and a transmission loss of the input signal can be reduced.

Abstract: A space portion is present between the upper surface of a semiconductor chip of a semiconductor chip mounted substrate fitted into a cavity (concave portion for setting) of a lower mold section and the top surface of a cavity of an upper mold section. The upper and lower mold sections are closed while a resin member having a thickness larger than the height of the space portion is inserted in the space portion. At this time, clamping force between the upper and lower mold sections is applied to the semiconductor chip through the resin member. The resin member is deformed in response to the shape of the space portion. Underfill is molded between the semiconductor chip and the substrate while the resin member adheres to both of the upper surface of the semiconductor chip and the top surface of the cavity of the upper mold section.

Abstract: The present invention is a bonding pad structure for improving impedance matching that can optimize the impedance matching of the loop between the chip and the substrate inside the package so as to improve the electrical characteristics of the package structure by increasing the capacitance of the loop through a simple structural refinement of the bonding pad structure. The aforesaid bonding pad structure has function of signal transmission and grounding for electronic components having multiple electrical-connected layers, furthermore, the feature of the foregoing structure is as following: the space between two bonding pads exists a metal structure constructed using a plurality of parallel-positioned metal layers which are overlapping and disconnected to one another.

Abstract: The present invention provides a pixel array and a process flow for forming an array of pixel cells that features pixel electrodes having overlapping edges. This overlapping pixel configuration precludes absorption of light in inter-pixel regions that could give rise to the appearance of dark lines between bright reflective pixel electrodes. This pixel arrangement also prevents the disruption of charge stored in underlying capacitor structures due to the penetration of incident light through inter-pixel regions into the underlying substrate.

Abstract: A fuse used for redundancy function in a semiconductor device includes a pair of fuse terminals formed as a common layer with top interconnect lines by using a damascene technique, and a fuse element made of refractive metal and bridging the fuse terminals. The fuse element is formed as a common layer with the protective cover films covering the interconnect lines.

Abstract: A method is provided for fabricating an SOI water. This may involve forming a silicon substrate and implanting oxygen into the substrate. Damaged portions of the implanted silicon may be healed/cured by CMP or anneal, for example. An epi layer may then be deposited over the healed/cured regions of the substrate. The substrate may then be annealed to form an insulative layer. The wafer may be thinned to provide the proper thickness of the epi layer.

Abstract: A multi-part lead frame die assembly is disclosed including a die bonded to a die paddle. A second lead frame including leads is superimposed and bonded onto the first lead frame. Also disclosed is a method for fabricating the multi-part lead frame assembly which utilizes equipment designed for single lead frame processing. If desired, the materials for the multi-part lead frame may be dissimilar.

Abstract: An optical coupling device includes: a light emitter provided on an input lead frame; a photoreceptor provided on an output lead frame; a load driving semiconductor element provided on a front surface of the output lead frame, and connected to the photoreceptor via the output lead frame; and a sealing resin section as a package for protecting the light emitter, the photoreceptor and the load driving semiconductor element, wherein a thermoelectric conversion element is provided in the package.

Abstract: This invention discloses a rectification chip terminal structure that mounts a rectification chip into a terminal by means of soldering and rubber injection, and inserts the chip into the pivotal hole on the printed wire board. Such terminal comprises a rib ring surrounding the terminal, a platform extended from the middle section of said terminal, a buffer groove formed between said platform and said rib ring, and a protruded ring extended from the periphery of said platform; when rubber is injected into the terminal, the rubber will go through the buffer groove and the protruded ring for the fixing action, and no air bubble will remain after the solidification of the rubber. It will increase the adhesive force between the rubber and the terminal, and also will increase the soldering area of the rectification chip, such that the space between the terminal and the rectification chip can be fully soldered to provide the best effect for a current flow with larger power.

Abstract: The invention includes a method of forming semiconductor circuitry wherein a first semiconductor structure comprising a first monocrystalline semiconductor substrate is bonded to a second semiconductor structure comprising a second monocrystalline semiconductor substrate. The first semiconductor substrate has a semiconductive material projection extending therefrom, and the second semiconductor substrate has an electrically conductive interconnect extending therethrough. The interconnect electrically connects with the semiconductive material projection, and comprises a different dopant type than the semiconductor material projection. The invention also includes a method of bonding a first monocrystalline semiconductor substrate construction to a second monocrystalline semiconductor substrate construction, wherein the first construction is doped to a first dopant type, and the second construction is doped to a second dopant type different from the first dopant type.

Abstract: In a semiconductor apparatus, a plurality of HBTs (heterojunction bipolar transistors) are formed on a front surface consisting of a (100) crystal plane of a GaAs substrate. Via holes passing thorough the GaAs substrate are formed in proximity of the HBTs. Each via hole has a rectangular-shaped hole edge at the front surface side of the GaAs substrate. The longitudinal direction of the hole edge on the surface side of the via hole is parallel to the [011] direction of crystal orientation of the GaAs substrate. A width of the via hole in a direction perpendicular to the [011] direction of crystal orientation is larger at the back surface of the substrate than at the front surface thereof.

Abstract: Light-emitting devices are described. One example of a light-emitting device includes a first barrier layer and a second barrier layer, and a quantum well layer located between the first and second barrier layers. The first and second barrier layers are composed of gallium arsenide, and the quantum well layer is composed of indium gallium arsenide nitride. A first layer is located between the quantum well layer and the first barrier layer. The first layer has a bandgap energy between that of the first barrier layer and that of the quantum well layer. Another example of a light-emitting device includes a quantum well and a carrier capture element adjacent the quantum well. The carrier capture element increases the effective carrier capture cross-section of the quantum well.

Abstract: A combination wafer is manufactured by (i) forming a plurality of alternating dielectric and metal layers, (ii) forming a guard ring trench in the layers, (iii) forming a guard ring layer in the guard ring trench, and then repeating (i), (ii) with a slightly wider guard ring trench, and (iii). A number of layers are thus simultaneously etched and lined with a guard ring layer, but the number of layers is not so large so as to cause lithographic problems that may occur when a deep, narrow guard ring trench is formed. An upper one of the layers that are patterned is always made of silicon dioxide, which includes less carbon than lower polymer layers and allows for a carbon mask to be formed and be easily removed. The slightly wider guard ring trench each time the process is repeated overcomes lithographic alignment problems that may occur when the guard ring trenches are exactly the same size. Subsequent guard ring layers are partially formed on one another, and provide a moisture seal.

Abstract: One aspect of the present invention relates to a method to facilitate formation of seed layer portions on sidewall surfaces of a trench formed in a substrate. The method involves the steps of forming a conformal seed layer over a barrier layer disposed conformal to a trench, wherein the trench is formed in the substrate; reflecting a light beam of x-ray radiation at the seed layer sidewall portions; generating a measurement signal based on the reflected portion of the light beam; and determining a thickness of the sidewall portions based on the measurement signal while the sidewall portions are being formed over the trench.

Abstract: In the component of a radiation detector, an upper end face of a pad formation protrusion provided on an upper surface of an MID substrate is equal in height to an upper surface of a photodiode array, first pads are provided on upper surfaces of photodiodes arranged in the photodiode array, respectively, second pads are provided on the upper end face of the pad formation protrusion, a bonding wire is provided between one of the first pads and corresponding one of the second pads, a wiring pattern is provided on the upper surface of the MID substrate, first terminals as many as the second pads and one second terminal are provided on a lower surface of the MID substrate, the second pads and the first terminals are electrically connected to one another in a one-to-one correspondence, and the wiring pattern is electrically connected to the second terminal.

Abstract: A method of manufacturing a micro-semiconductor element comprising the following steps of: adhering a semiconductor wafer 10 having a circuit surface and a back surface to a support plate 20 via a protective film 22 so that the circuit surface faces to the protective film; reducing a thickness of the semiconductor wafer while the semiconductor wafer is supported by the support plate; dividing the semiconductor wafer into individual semiconductor elements 10a while the semiconductor wafer is adhered to the protective film; moving the semiconductor elements from the protective film to an adhesive peeling film 26 in such a manner that the back surfaces of the semiconductor elements are adhered to the peeling film; supporting a periphery of the peeling film by a support ring 28; and picking up the individual semiconductor element by a pickup device when the back surface of semiconductor element is pushed up, via the peeling film, by a pushup pin 30.

Abstract: A method for forming a semiconductor device having a trench top isolation layer. A collar insulating layer is formed over a lower portion of the sidewall of the trench formed in a substrate. A first conductive layer is formed in the lower portion of the trench and protrudes the collar insulating layer, and a second conductive layer is formed overlying the first conductive layer and covers the collar insulating layer. An insulating spacer is formed over an upper portion of the sidewall of the trench and separated from the second conductive layer by a gap. The second conductive layer is partially thermally oxidized to form an oxide layer thereon whereby the gap is filled. After the oxide layer is removed, a reverse T-shaped insulating layer is formed thereon by chemical vapor deposition to serve as a trench top isolation layer. Finally, the insulating spacer is removed.

Abstract: A method of driving a dual-gated MOSFET having a Miller capacitance between the MOSFET gate and drain includes preparing the MOSFET to switch from a blocking mode to a conduction mode by applying to the MOSFET shielding gate a first voltage signal having a first voltage level. The first voltage level is selected to charge the Miller capacitance and thereby reduce switching losses. A second voltage signal is applied to the switching gate to switch the MOSFET from the blocking to the conduction mode. The first voltage signal is then changed to a level selected to reduce the conduction mode drain-to-source resistance and thereby reduce conduction losses. The first voltage signal is returned to the first voltage level to prepare the MOSFET for being switched from the conduction mode to the blocking mode.

Abstract: A supporting structure is wafer-bonded to the upper face side of a partially or fully processed device wafer. The device wafer includes a transistor having a well region that extends into the substrate material of the device wafer. The source and drain regions of the transistor extend into the well region. After attachment of the supporting structure, the device wafer is thinned from the back side until the bottom of the well region is reached. To reduce source and drain junction capacitances, etching can continue until the source and drain regions are reached. In one embodiment, all of the well-to-substrate junction is removed in a subsequent etching step, thereby reducing or eliminating the well-to-substrate junction capacitance of the resulting transistor. Resistance between the well electrode and the transistor channel is reduced because the well contact is disposed on the back side of the device wafer directly under the gate of the transistor.