Abstract: The wiring board 1 is provided with the first resin insulating layer 7, the first filled via 19 penetrating it and filled and formed by the plating, and the second conductor layer 29 formed by the plating on them. In them, the second conductor layer 29 comprises the first resin insulating layer 7, the electroless plating layer 33 formed on the first filled via 19, and the electrolytic plating layer 37 composed of plating particle of substantially uniform size, formed thereon.

Abstract: Solder balls, such as, low melt C4 solder balls undergo volume expansion during reflow. Where the solder balls are encapsulated, expansion pressure can cause damage to device integrity. A volume expansion region in the semiconductor chip substrate beneath each of the solder balls accommodates volume expansion. Air-cushioned diaphgrams, deformable materials and non-wettable surfaces may be used to permit return of the solder during cooling to its original site. A porous medium with voids sufficient to accommodate expansion may also be used.

Abstract: The present invention provides a particle or electromagnetic radiation sensor structure, comprising a substrate (13) having a major surface and a sensitive layer (16) on the major surface of the substrate (13), the sensitive layer (16) being sensitive to particle or electromagnetic radiation and having a first surface (17) remote from the substrate (13). The sensitive layer (16) has a doping concentration gradient from a higher doping level to a lower doping level, the doping concentration decreasing from the substrate (13) to the first surface (17) of the sensitive layer (16). According to an embodiment, over any distance across the sensitive layer (16) which is half of the thickness of the sensitive layer (16), the ratio between the highest doping level and the lowest doping level is at least a factor 2, preferably at least a factor 3 or more. The present invention also provides a method for obtaining such a sensor structure, as well as arrays comprising such sensor structures.

Abstract: A semiconductor device includes a silicon semiconductor substrate, having a main surface including a first region and a second region side-by-side, an epitaxially grown layer of high resistivity as a first layer on the main surface, and an epitaxially grown layer of low resistivity as a second layer on the first layer, and having a resistivity lower than the resistivity of the first layer. The semiconductor device includes a bipolar transistor at the first region and a passive element at the second region. The second layer is covers at least the first region and is absent from at least a portion of the second region.

Abstract: In an integrated circuit device, third transistors having the thickest gate insulation film are driven at high voltage and thus operate at high speed with minimal gate leak current. First transistors having the thinnest gate insulation film and second transistors which do not have the thinnest gate insulation film are driven at low voltage, the second transistors being driven at all times and the first transistors being halted as appropriate. The second transistors operate constantly at low speed and with minimal gate leak current, and the first transistors, which have significant gate leak current, operate at high speed while halting as appropriate.

Abstract: A cost effective method is provided for assembly of hybrid optoelectronic circuits requiring flip-chip bonding of multiple active optoelectronic devices onto common substrate or optical bench platform with fine pitch and high accuracy “after-bonding” alignment to the alignment features on substrate and/or to other elements of the hybrid circuit. A Flip-Chip Bonder equipped with high precision Bonding Arm and optical and mechanical system, heated substrate chuck and heated pick-up tool may be used both for alignment and thermal bonding of active component dies to corresponding bonding pads on the common substrate using gold-tin (Au—Sn) solder disposed between die bonding pad and the corresponding substrate bonding pad.

Abstract: The present invention provides a method for forming an antifuse via structure. The antifuse via structures comprising a substrate that having a first conductive wire therein. Then, a first dielectric layer is formed on the substrate, and a photoresist layer is formed on the first dielectric layer. Next, an etching process is performed to etch the first dielectric layer to form a via open in the first dielectric layer. Then, a first conductive layer is deposited to fill the via open and performing a polishing process to form a conductive plug, wherein the conductive plug is on the first conductive wire. Next, a buffer layer deposited on the partial first dielectric layer and on the surface of conductive plug. Then another polishing process is performed to the buffer layer to expose the portion of the conductive plug. Thereafter, a first electrode of capacitor is deposited on the buffer layer.

Abstract: A modular blood filter apparatus and methods of use. The modular filter apparatus includes an adjustable frame capable of assuming enlarged and contracted conditions and a frame sizing mechanism associated with the frame. Certain embodiments include a filter cartridge to protect the adjustable filter device therein. The cartridge may be removably introduced into a blood vessel, and the adjustable filter device may be deployed through the device into the vessel. The adjustable frame may be self-adjusting or externally adjusted to fit the vessel and to capture embolic material in the filter. The frame may be collapsed to the contracted condition, and may be removed from the vessel.

Abstract: A circuit is described which has a semiconductor component surrounded by a plastic housing and with which contact can be made via conductor tracks. Between each dividing surface of the conductor tracks and an area of the plastic housing surrounding the relevant dividing surface, as viewed in plan view of the dividing surface, a spacing is provided in each case.

Abstract: The invention relates to a transfer and support device for a double-sided panel, in particular a printed circuit panel. The device comprises a bottom slab having a top reference surface that is plane and horizontal for receiving the bottom face of panel; a top slab having a bottom reference surface that is plane and horizontal for receiving the top face of panel; and for moving slabs separately in two respective horizontal planes, each of being provided with controllable for pressing a face of panel against the reference surface of slab when they are activated. The device also has controllable for lifting panel.

Abstract: A light-emitting device comprises a substrate, electrical terminals disposed on a top side of the substrate, and a light-emitting semiconductor device disposed above the substrate. The light-emitting semiconductor device has a bottom side oriented to face toward the top side of the substrate. Electrodes are disposed on the bottom side of the light-emitting semiconductor device and electrically connected to the terminals on the substrate. A glass layer is arranged in a path of output light emitted by the light-emitting semiconductor device. The glass layer contains fluorescent material that converts at least a portion of the output light to converted light having a wavelength different from a wavelength of the output light. The fluorescent material may include SrS:Eu2+ that emits red light and (Sr, Ba, Ca)Ga2S4:Eu2+ that emits green light.

Abstract: A semiconductor device comprises fuse elements formed on an insulating interlayer over a semiconductor substrate. A groove is formed in the insulating interlayer at each space between the fuse elements. A silicon nitride film of a predetermined thickness covers the side and upper surfaces of each fuse element. Since the side and upper surfaces of each fuse element are covered with the silicon nitride film of the same thickness, the film covering the fuse elements has no local weak point. Consequently, when a fuse element is blown out by applying laser beams, it is prevented that the silicon nitride film breaks before the temperature of the fuse element fully rises, and melted fuse element flows out.

Abstract: In a leadframe for an LGA package, a lead member is pressed downward to form a land lead with a half-cut portion and a land portion. The land portion, whose bottom will be a land electrode, is inclined at a predetermined angle and the bottom of the land portion is made lower than that of a lead. Thus, in a resin molding process using a seal sheet, the land electrode is forced into, and strongly adhered to, the seal sheet when pressure is applied through dies, and no resin encapsulant reaches the land electrode. As a result, no resin bur will be left on the land electrode of the land lead.

Abstract: Improvements to chemical vapor deposition processes are taught for depositing tungsten nitride in semiconductor manufacturing processes. In one irmproved process NF3 is used as a source of nitrogen, and a plasma is introduced under controlled conditions to control particle formation and lower the temperature at which acceptable films may be produced. In another set of processes substantially pure tungsten is produced by rapid thermal annealing of substantially amorphous tungsten nitride at temperatures lower than achieved in the art, by using hydrogen in the ambient atmosphere. In yet another set of new processes particle formation and step coverage enhancement when using NH3 as a nitrogen source is controlled by limiting the pressure at which source gases mix, by unique wall coating technique, and by controlling chamber wall temperature.

Abstract: To a provide a method of forming a layered film of a silicon nitride film and a silicon oxide film on a glass substrate in a short time without requiring a plurality of film deposition chambers. In a thin film transistor, a layered film including a silicon nitride oxide film (12) is formed between a semiconductor layer (13) and a substrate (11) using the same chamber. The silicon nitride oxide film has a continuously changing composition ration of nitrogen or oxygen. An electric characteristic of the TFT is thus improved.

Abstract: A non-volatile memory includes a substrate: a floating gate electrode and a control gate electrode formed on the substrate; and an active layer formed around the control gate and the floating gate. The active layer has source and drain and a channel layer between the source and drain.

Abstract: A pixel sensor system includes a photo-sensor, an output amplifier, and a feedback capacitor. The photo-sensor is configured to receive photons and to convert the photons into charge. The output amplifier has at least two transistors in a cascoded configuration. The amplifier converts the charge into electronic signal. The feedback capacitor is disposed between the photo-sensor and an input of the output amplifier.

Abstract: A semiconductor device including a semiconductor integrated circuit chip having a semiconductor substrate, a plurality of chip pads positioned on a surface of the substrate, a passivation layer formed on the substrate and having openings to expose the chip pads. A first polymer layer is formed on the passivation layer, a patterned first under barrier metal (UBM) layer formed on the chip pads and the first polymer layer, a plurality of redistribution pattern formed on the first UBM, with each redistribution pattern having a concave pattern in a bump pad area. A second polymer layer is formed on the first polymer layer and the redistribution pattern, the second polymer layer having openings for exposing the bump pad areas, a second under barrier metal (UBM) formed on the bump pads. A plurality of solder bumps is formed on the second UBM and electrically connected to the redistribution pattern in the bump pad area.

Abstract: Fabrication of a CSP or a stacked chip CSP can be accomplished with an unsupported film adhesive or an adhesive supported on a rigid carrier, using standard die attach equipment constructed for use with a paste adhesive.

Abstract: A method of manufacturing a semiconductor device, includes the steps of forming a disposable gate on a semiconductor substrate in a region where a gate electrode is to be formed, forming a sidewall spacer on a sidewall of the disposable gate, forming a source and drain in the semiconductor substrate using the disposable gate and the sidewall spacer as a mask, forming an interlevel insulating film on the semiconductor substrate so as to cover the disposable gate, planarizing an upper surface of the interlevel insulating film to expose upper surfaces of the disposable gate and the sidewall spacer, removing the disposable gate to form a trench portion having a side surface formed from the sidewall spacer and a bottom surface formed from the semiconductor substrate, depositing a gate insulating film on the semiconductor substrate so as to cover the bottom surface and side surface of the trench portion, forming a gate electrode buried in the trench portion, and removing the sidewall spacer and the gate insulating