Abstract: Through-holes are inserted in the substrate of an LED matrix to increase air circulation and cooling. Fans may be used to increase cooling.

Abstract: A capacitor of a semiconductor device is provided which includes a semiconductor substrate and insulating interlayer formed on the semiconductor substrate. The insulating interlayer has a contact hole which exposes a portion of the semiconductor substrate. A plug fills in the contact hole and the plug comes into contact with the semiconductor substrate. A contact layer is formed on the insulating interlayer. The contact layer comes into contact with the plug. First and second barrier layers are formed on the surface and sides of the contact layer, and a lower electrode is formed on the first barrier layer. A dielectric layer formed on the second barrier layer and lower electrode, and an upper electrode is formed on the dielectric layer.

Abstract: The present invention discloses a method for fabricating a semiconductor device. A stabilized junction is formed by simultaneously adjusting diffusion in a channel direction and a depth direction by restricting transient enhanced diffusion and oxidation enhanced diffusion, and reducing a short channel effect and diffusion in the depth direction, by positioning a nitrified oxide film between a gate electrode and a nitride film spacer formed at side walls of the gate electrode in order to remove defects generated due to stress differences between the gate electrode and the nitride film spacer in a formation process of a PMOS transistor. It is thus possible to form a device having an ultra shallow junction which is not influenced by miniaturization.

Abstract: A method of producing a contact structure for establishing electrical connection with contact targets. The contact structure is formed of a contactor carrier and a plurality of contactors. The contactor has an upper end oriented in a vertical direction, a straight beam portion oriented in a direction opposite to the upper end and having a lower end which functions as a contact point for electrical connection with a contact target, a return portion returned from the lower end and running in parallel with the straight beam portion to create a predetermined gap therebetween, a diagonal beam portion provided between the upper end and the straight beam portion to function as a spring.

Abstract: A semiconductor chip includes a semiconductor substrate having a rectifying contact diffusion and a non-rectifying contact diffusion. A halo diffusion is adjacent the rectifying contact diffusion and no halo diffusion is adjacent the non-rectifying contact diffusion. The rectifying contact diffusion can be a source/drain diffusion of an FET to improve resistance to punch-through. The non-rectifying contact diffusion may be an FET body contact, a lateral diode contact, or a resistor or capacitor contact. Avoiding a halo for non-rectifying contacts reduces series resistance and improves device characteristics. In another embodiment on a chip having devices with halos adjacent diffusions, no halo diffusion is adjacent a rectifying contact diffusion of a lateral diode, significantly improving ideality of the diode and increasing breakdown voltage.

Abstract: A bipolar transistor device with a large current capacity is formed by connecting a plurality of transistor elements to each other in parallel, each transistor element having a collector layer, a base layer, and an emitter layer formed respectively in a semiconductor substrate. In the bipolar transistor device, the base layers of a plurality of the transistor elements are extended in parallel to each other and those base layers are separated from each other. In each separated base layer, a first base electrode is formed on a part of the base layer which is separated from an emitter junction with the emitter layer, and a second base electrode is formed on another portion of the base layer closer to the emitter junction than the first base electrode. To dispose the base electrodes of a plurality of the transistor elements in parallel to each other, a base wiring is connected to the first base electrodes of those elements electrically.

Abstract: A barrier stack for sealing devices is described. The barrier stack includes at least first and second base layers bonded together with a high barrier adhesive. A base layer includes a flexible support coated on at least one major surface with a barrier layer. The adhesive advantageously seals defects, such as pinholes in the barrier layer, thus improving the barrier properties.

Abstract: In a method of manufacturing a thin film transistor, in a first deposition step a light shield film is deposited on a substrate. In a second deposition step a semiconductor film is deposited for forming a channel of the transistor on the light shield film. In a patterning step the light shield film and the semiconductor film are simultaneously shaped into the same shape pattern. In an electrode forming step a source electrode and a drain electrode which are respectively in contact with both end-portions of the shaped semiconductor film are formed. An insulator film is formed so that the insulator film covers the source and drain electrodes and the semiconductor film. A gate electrode is formed at a location on the insulator film corresponding to the semiconductor film.

Abstract: A micro grid array semiconductor die package includes a housing defining a cavity for holding at least one semiconductor die, said housing including a plurality of insulative side walls, each of said side walls having a bottom surface and an interior wall including a top surface, and an end plate joined to said side walls; and a plurality of substantially straight conductive leads extending through at least one of said side walls, each of said conductive leads including an internal lead section extending into the cavity from the top surface of the interior wall and a external lead section extending externally from said at least one bottom surface of said side wall.

Abstract: A method of forming bumps on the active surface of a silicon wafer. A first under-ball metallic layer is formed over the active surface of the wafer. A second under-ball metallic layer is formed over the first under-ball metallic layer. A portion of the second under-ball metallic layer is removed to expose the first under-ball metallic layer. A plurality of solder blocks is implanted over the second under-ball metallic layer. A reflux operation is conducted and then the exposed first under-ball metallic layer is removed so that only the first under-ball metallic layer underneath the second under-ball metallic layer remains.

Abstract: A method of forming a TFT-LCD device with a rough pixel electrode is disclosed. The method comprises the following steps. First, a photosensitive layer is formed on the transparent insulating substrate. A defocused exposing procedure is then performed by applying a mask with plural independent spot patterns and a contact hole pattern to define patterns on the photosensitive layer. Notedly the distance between two adjacent independent spot patterns is smaller than the resolution of exposure system. Thus the area of photosensitive layer corresponding to independent spot patterns is exposed incompletely. Then the photosensitive layer is developed to remove partial photosensitive layer to form wave-like surfaces thereon. Next a pixel electrode is formed on the photosensitive layer to have rising and falling surfaces with the photosensitive layer to serve as a rough diffuser member.

Abstract: A method for forming a dual damascene interconnect in a dielectric layer is provided. Generally, a first aperture is etched in the dielectric. A poison barrier layer is formed over part of the dielectric, which prevents resist poisoning. A patterned mask is formed over the poison barrier layer. A second aperture is etched into the dielectric layer, wherein at least part of the first aperture shares the same area as at least part of the second aperture.

Abstract: An integrated circuit is provided with high-aspect ratio vias in which the upper channel after lining with an adhesion/barrier layer is used as a collimator with a via entrant angle of greater than about 70 degrees during the ionized metal plasma deposition of the seed layer over the adhesion/barrier layer. This results in a seed layer with reduced overhang in the vias enhancing the subsequent filling of the vias by a conductive layer and preventing the formation of voids in the vias.

Abstract: A method of manufacturing a microelectronic assembly includes providing a first microelectronic element having a first surface and a plurality of terminals exposed at the first surface, providing a second microelectronic element having a top surface and a plurality of contacts exposed at the top surface, forming a plurality of conductive elastomeric posts which connect each of the contacts to one of the terminals, and injecting a compliant material between the first surface of the first microelectronic element and the top surface of the second microelectronic element to form a compliant layer.

Abstract: A method of manufacturing a MOSFET semiconductor device includes forming a gate electrode oxide over a substrate; depositing a first layer of polysilicon over the gate oxide; implanting dopants in the first layer; depositing a second layer of polysilicon over the first layer; etching both layers to form a gate electrode; forming source/drain extensions in the substrate; forming first and second sidewall spacers; implanting dopants within the substrate to form source/drain regions in the substrate; and laser thermal annealing to activate the source/drain regions and to melt the first layer. The first layer can have a depth of about 200 to 500 angstroms, and the second layer can have a depth of about 300 to 4500 angstroms. The source/drain extensions can have a depth of about 50 to 300 angstroms, and the source/drain regions can have a depth of about 400 to 1000 angstroms. The laser thermal annealing can also melt amorphitized portions of the second layer.

Abstract: A silicon-on-insulator(SOI) transistor. The SOI transistor having a source and a drain having a body disposed therebetween, the source being implanted with germanium to form an area of silicon-germanium adjacent a source/body junction in a lower portion of the source, the area of silicon-germanium in the source forming a hereto junction along a lower portion of the source/body junction.

Abstract: A light emitting diode device has a reflector member having an approximately semispherical recess. A reflector surface is provided on an inner surface of the recess and a light emitting diode is provided in the recess. The light emitting diode is located at a position so that a part of light beams emitted from the light emitting diode recedes from an optical axis, and another part of the light beams approaches to the optical axis.

Abstract: The present invention relates to the planarization of surfaces as typically encountered in the fabrication of integrated circuits, particularly copper conductors and Ta/TaN barrier layers encountered in damascene and dual damascene interconnects. The present invention describes planarization methods for Cu/Ta/TaN interconnects, typically making use of a viscous overlayer tending to dwell in regions of lower surface topography, protecting said lower regions from etching by a combination of chemical and mechanical effects. In some embodiments, the viscous overlayer contains species that hinder removal of copper from regions of the surface in contact with the viscous layer. Such species may be a substantially saturated solution of copper ions among other additives, thereby hindering the dissolution of interconnect copper into the protective overlayer.

Abstract: A process for the fabrication of an integrated circuit which provides a FET device having reduced GIDL current is described. A semiconductor substrate is provided wherein active regions are separated by an isolation region, and a gate oxide layer is form on the active regions. Gate electrodes are formed upon the gate oxide layer in the active regions. An angled, high dose, ion implant is performed to selectively dope the gate oxide layer beneath an edge of each gate electrode in a gate-drain overlap region, and the fabrication of the integrated circuit is completed.

Abstract: A nitride semiconductor device is composed of Group III nitride semiconductors. The device includes an active layer, and a barrier layer made from a predetermined material and provided adjacent to the active layer. The barrier layer has a greater band-gap than that of the active layer. The device also includes a barrier portion formed of the predetermined material for surrounding a threading dislocation in the active layer. The barrier portion has a vertex. The device also includes a semiconductor layer having an impurity concentration ranging from 1E16/cc to 1E17/cc in which the vertex is placed.