Abstract: The present invention of a purplish pink light emitting diode irradiates a purple light with a wavelength ranging from 405 to 430 nm of a LED chip of a light emitting diode onto a red fluorescent powder coated on the surface thereon such that the purple light excites the fluorescent powder to produce a red light with a wavelength about 650 nm. The mixture of the excited red light and the original purple light from the purple light emitting diode produces a purplish pink or pinkish red light emitting diode in a new color tone with extensive application. To use the neoteric and unique color (similar to the color of a Hello Kitty) as a backlight or for displaying or illumination on electronic merchandises, such as mobile phones, attracts the consumers of the young generation.

Abstract: An electron beam exposure method is described which provides a means of curing spin-on-glass or spin-on-polymer dielectric material formed on a semiconductor wafer. The dielectric material insulates the conductive metal layer and planarizes the topography in the process of manufacturing multilayered integrated circuits. The method utilizes a large area, uniform electron beam exposure system in a soft vacuum environment. A wafer coated with uncured dielectric material is irradiated with electrons of sufficient energy to penetrate the entire thickness of the dielectric material and is simultaneously heated by infrared heaters. By adjusting the process conditions, such as electron beam total dose and energy, temperature of the wafer, and ambient atmosphere, the properties of the cured dielectric material can be modified.

Abstract: Disclosed herein is a surface mounting method for high power output light emitting diode (LED). In the first preferred embodiment, the LED is mounted onto a thermal & electrical base-substrate, which has a plurality of trenches formed therein and filled with an insulating layer to isolate two parts of the base-substrate. A reflective frame assembler having a plurality of reflective frame is then adhered to the upper surface of the base-substrate. Each of them is for placing one LED chip. After a LED is with its two electrodes placed on a pair of the first metal contacts, the transparent resin or epoxy is refilled into reflective frame to seal the LED chip. In the second preferred embodiment, the LED is with two electrodes on the different side. Hence the LED is mounted on one metal contact only, the other electrode is in terms of a wire to bond to the other metal contact.

Abstract: A process is described for semiconductor device integration at chip level or wafer level, in which vertical connections are formed through a substrate. A metallized feature is formed in the top surface of a substrate, and a handling plate is attached to the substrate. The substrate is then thinned at the bottom surface thereof to expose the bottom of the feature, to form a conducting through-via. The substrate may comprise a chip having a device (e.g. DRAM) fabricated therein. The process therefore permits vertical integration with a second chip (e.g. a PE chip). The plate may be a wafer attached to the substrate using a vertical stud/via interconnection. The substrate and plate may each have devices fabricated therein, so that the process provides vertical wafer-level integration of the devices.

Abstract: The several embodiments of the invention provide for formation of gate electrode structures with recessed and partially recessed spacers. One embodiment, provides a gate electrode structure with recessed thick inner spacers and thick outer spacers. Another embodiment provides a gate electrode structure with recessed thin inner spacers and recessed thick outer spacers. Another embodiment provides a gate electrode structure with thin inner spacers and partially recessed outer spacers. Another embodiment provides a gate electrode structure with two spacer stacks. The outermost spacer stack with recessed thin inner spacers and recessed thick outer spacers. The inner spacer stack with thin inner spacers and thin outer spacers. Another embodiment provides a gate electrode structure with two spacer stacks. The outermost spacer stack with recessed thin inner spacers and recessed thick outer spacers. The inner spacer stack with recessed thin inner spacers and recessed thin outer spacers.

Abstract: A memory cell having a transistor and a capacitor formed in a silicon substrate. The capacitor is formed with a lower electrically conductive plate etched in a projected surface area of the silicon substrate. The lower electrically conductive plate has at least one cross section in the shape of a vee, where the sides of the vee are disposed at an angle of about fifty-five degrees from a top surface of the silicon substrate. The surface area of the lower electrically conductive plate is about seventy-three percent larger than the projected surface area of the silicon substrate in which the lower electrically conductive plate is etched. A capacitor dielectric layer is formed of a first deposited dielectric layer, which is disposed adjacent the lower electrically conductive plate. A top electrically conductive plate is disposed adjacent the capacitor dielectric layer and opposite the lower electrically conductive plate.

Abstract: A double-gate field effect transistor (DGFET) is provided using a damascene-like replacement gate processing step to create sidewall source/drain regions, oxide spacers and gate structures inside a previously formed trench. The damascene-like replacement gate processing step allows for the fabrication of a tapered transistor body region having a thicker body under the contacts which reduces access resistance.

Abstract: An antireflection coating (ARC) polymer layer is patterned by DUV (deep ultraviolet) lithography followed by an ARC open etching step and subsequent etching of the metal layer. Low resist consumption and hence steeper resist sidewalls are achieved by virtue of the ARC polymer intermediate layer being etched with a CF4 ARC open process with high selectivity with respect to the photoresist. The gas flows are set to the following ranges: CF4 35-45 sccm, CHF3 17-23 sccm, O2 5-7 sccm and Ar 80-120 sccm.

Abstract: A thrombus filter configured for placement in within a blood vessel lumen defined by a blood vessel wall. Methods and devices for selectively removing the thrombus filter when the presence of a filter in the vascular system is no longer desired. The thrombus filter includes a first strand formation, a second strand formation, and a joined portion.

Abstract: A semiconductor device comprises a first conductivity type semiconductor substrate, a first conductivity type semiconductor layer formed on the substrate, a MISFET formed in a first area of the semiconductor layer, having a drain and source, and a gate electrode formed on a semiconductor layer between the drain and source through a gate insulator, an internal source electrode formed to contact the source and whose surface is covered with an insulating layer, a diode formed in a second area of the semiconductor layer, having a cathode and an anode provided on the cathode, an anode electrode which contacts the anode, a conductive portion piercing the semiconductor layer to electrically connect the internal source electrode and the cathode to the substrate, and a source/cathode electrode formed on the back plane of the substrate and commonly provided as a source electrode of the MISFET and a cathode electrode of the diode.

Abstract: An encapsulated microelectronic device. The device includes a semiconductor substrate, microelectronic device adjacent to the semiconductor substrate, and at least one first barrier stack adjacent to the microelectronic device. The barrier stack encapsulates the microelectronic device. It includes at least one first barrier layer and at least one first polymer layer. The encapsulated microelectronic device optionally includes at least one second barrier stack located between the semiconductor substrate and the microelectronic device. The second barrier stack includes at least one second barrier layer and at least one second polymer layer. A method for making an encapsulated microelectronic device is also disclosed.

Abstract: When a plasma is ignited in a plasma generator, an ion beam is made to run in the plasma generator, and in this state, a positive voltage with respective to ground is applied to a plasma production chamber from a DC power source. Secondary electrons are generated when the ion beam collides with a plasma generating gas which flows out of the plasma production chamber into a path of the ion beam. The secondary electrons are led into the plasma production chamber by the positive voltage, and within the plasma production chamber, a plasma ignition is triggered using the secondary electrons led into the plasma production chamber and a radio frequency.

Abstract: Semiconductor devices in an optoelectronic integrated circuit are electrically isolated from each other by using planar lateral oxidation to oxidize a buried semiconductor layer vertically separating the semiconductor devices.

Abstract: A connector for use in providing an anastomotic connection between two tubular body fluid conduits in a patient. The connector is preferably a single, integral, plastically deformable structure that can be cut from a tube. The connector has axial spaced portions that include members that are radially outwardly deflectable from other portions of the connector. The connector is annularly enlargeable so that it can be initially delivered and installed in the patient in a relatively small annular size and then annularly enlarged to provide the completed anastomosis. The radially outwardly deflected members of the first and second portions respectively engage the two body fluid conduits connected at the anastomosis and hold those two conduits together in fluid-tight engagement. Apparatus for use in delivering and deploying a connector is also disclosed.

Abstract: The invention is directed to a catheter formed at least in part of a multilayered member having a first layer which is fusion bondable to another catheter component such as the skirt of an inflatable balloon and a second layer which is adjacent the first layer having a melting point greater than the first layer so that the multilayered member of the catheter is not deformed when the other catheter component is fusion bonded to the first layer of the multilayered member. The second layer is preferably lubricious in nature. In one embodiment of the invention, the multilayered member is a tubular element with the lubricious second layer defining an inner lumen extending within the tubular element. The outer layer of the tubular member may extend beyond the distal end of the inner layer and form a non-traumatic distal tip. Alternatively, a flexible non-traumatic distal tip may be fusion bonded to at least the outer layer of the multilayered tubular member.

Abstract: A surgical device for cutting substantially across a cornea of an eye of a patient, the device including a positioning ring structured to be temporarily attached to a portion of the eye surrounding the cornea to be cut, and defining an aperture sized to receive and expose the cornea to be cut. The surgical device further includes a cutting head assembly structured to be guided and driven over an upper surface of the positioning ring in a generally arcuate path, and having a cutting element positioned therein and structured to oscillate laterally to facilitate smooth and effective cutting of the cornea. The cutting head assembly is structured to be detachably coupled to the positioning ring by a coupling member which permits movement of the cutting head assembly relative to the positioning ring along the generally arcuate path, but maintains sufficient engagement therebetween to ensure that smooth, steady, driven movement is maintained.

Abstract: An improved buried strap method in the fabrication of a DRAM integrated circuit device where the active area is self-aligned to the deep trench in the length direction only is described. An etch stop layer is provided on a substrate. A deep trench is etched into the substrate not covered by the etch stop layer and filled with a silicon layer to form a deep trench capacitor. A polysilicon layer is deposited over the capacitor to form a buried strap. A liner layer is deposited over the etch stop layer and the buried strap having the same material as the etch stop layer. A hard mask material is deposited over the liner layer and etched where it is not covered by a mask wherein etching stops at the liner layer. The liner layer and the etch stop layer are etched away where they are not covered by the hard mask layer to form an etch stop frame. The substrate and the deep trench are etched into where they are exposed by the hard mask and the etch stop frame to form isolation trenches.

Abstract: Unfavorable interactions of ferroelectric dielectric layers with silicon, intermetallic dielectrics, and other materials in metal-oxide semiconductor devices have discouraged the use of ferroelectric memory devices. This invention provides a zirconium titanate barrier layer with high insulating and low leakage characteristics. The barrier layer is not reactive with silicon or other materials used in metal-ferroelectric-semiconductor devices. These thermally stable layers should facilitate the integration of ferroelectric materials into memory and other semiconductor devices.

Abstract: The present invention is directed to a fastener assembly for use during a surgical procedure for securing a first component to a second component. The fastener assembly includes a fastening assembly for securing the first component to the second component under a force. The fastening assembly has a first portion located on one side of the first component and the second component, a second portion located on another side of the first component and the second component, and an intermediate portion connecting to the first portion and the second portion. The intermediate portion extends through the second component and the first component. The first portion, the second portion and the intermediate portion act to apply a compressive force to the first component and the second component to secure the first component to the second component. In accordance with the present invention, at least one of the first portion, the second portion and the intermediate portion of fastening assembly is flexible.

Abstract: Semiconductor device and method for manufacturing the same prevent the spread of a tungsten film out of an opening portion of a contact hole when the tungsten is grown in the contact hole and avoid inferior wiring shape and inter-wiring shirt-circuit. After a titanium/titanium nitride film is formed along an inner surface of the contact hole, a photo-resist film is applied. Then, the photo-resist film is etched away until a distance from an upper end of the contact hole to the surface of photo-resist film is not smaller than one-half of a width of the contact hole when the titanium/titanium nitride film is formed. After the titanium/titanium nitride film is etched by using the photo-resist as a mask, the photo-resist film is removed and a tungsten layer is selectively grown by using the titanium/titanium nitride film as a seed.