Abstract: A method for forming a memory device includes: after a hard mask layer is formed on a semiconductor substrate, a plurality of parallel mask patterns extending along a third direction are formed on the semiconductor substrate by adopting a self-alignment multi- pattern process, an opening is provided between the adjacent mask patterns, and the opening exposes surfaces of a plurality of drain regions and corresponding isolation layers in the third direction.

Abstract: A display apparatus includes: a base substrate including a display area, an opening area, and an opening peripheral area between the opening area and the display area, wherein the display area surrounds the opening area, and the opening peripheral area has an annular shape; a conductive pattern disposed on the base substrate in the opening peripheral area and having an annular shape; and a light emitting layer disposed on the base substrate and in a portion of the opening peripheral area, and including an organic material, and wherein the light emitting layer is not formed at a portion of opening peripheral area that is adjacent to the opening area.

Abstract: A method for manufacturing an electronic device includes the following steps. A substrate including a first region and a second region is provided. A seed layer is formed on the substrate. A circuit structure layer is formed on the seed layer, and the circuit structure layer has a plurality of first circuit structures disposed on the first region and a plurality of second circuit structures disposed on the second region. The first circuit structures and the second circuit structures are electrically connected through the seed layer. A circuit test process is performed and includes applying a predetermined voltage to the second circuit structures to test the first circuit structures to determine whether the first circuit structures are normal or not.

Abstract: The invention concerns a device comprising a support, an electrically-conductive layer covering the support, a semiconductor substrate on the conductive layer, and an insulating casing.

Abstract: A highly portable and highly browsable light-emitting device is provided. A light-emitting device that is less likely to be broken is provided. The light-emitting device has a strip-like region having high flexibility and a strip-like region having low flexibility that are arranged alternately. In the region having high flexibility, a light-emitting panel and a plurality of spacers overlap with each other. In the region having low flexibility, the light-emitting panel and a support overlap with each other. When the region having high flexibility is bent, the angle between normals of facing planes of the two adjacent spacers changes according to the bending of the light-emitting panel; thus, a neutral plane can be formed in the light-emitting panel or in the vicinity of the light-emitting panel.

Abstract: The present disclosure relates to a solid-state image pickup device and an electronic apparatus that are capable of preventing leakage of charges between adjacent pixels. A plurality of pixels perform photoelectric conversion on light incident from a back surface via different on-chip lenses for each pixel. A pixel separation wall is formed between pixels adjacent to each other, and includes a front-side trench formed from a front surface and a backside trench formed from the back surface. A wiring layer is provided on the front surface. The present disclosure is applicable to, for example, a backside illuminated CMOS image sensor.

Abstract: Aspects of the present disclosure provide 3D semiconductor apparatus and a method for fabricating the same. The 3D semiconductor apparatus can include a first semiconductor device including first S/D regions, a first gate region sandwiched by the first S/D regions, and a first channel surrounded by the first S/D regions and the first gate region; a second semiconductor device stacked on the first semiconductor device that includes second S/D regions, a second gate region sandwiched by the second S/D regions, and a second channel surrounded by the second S/D regions and the second gate region and formed vertically in-situ on the first channel; and silicide formed between the first and second semiconductor devices where the first and second channels interface and coupled to an upper one of the first S/D regions of the first semiconductor device and a lower one of the second S/D regions of the second semiconductor device.

Abstract: A semiconductor device includes: a substrate including a cell area and an interface area; a gate electrode disposed in the substrate within the cell area and extending in a first direction; a plurality of bit lines intersecting the gate electrode and extending in a second direction intersecting the first direction, wherein the plurality of bit lines includes a plurality of first bit lines and a plurality of second bit lines alternately disposed in the first direction; edge spacers disposed within the interface area and contacting the plurality of second bit lines; and edge insulating layers disposed between the edge spacers and contacting the plurality of first bit lines, wherein at least a portion of each of the edge insulating layers is disposed within the interface area.

Abstract: Memory devices and methods of forming memory devices are described. Methods of forming electronic devices are described where a spacer is formed around each of the bit line contact pillars, the spacer in contact with the spacer of an adjacent bit line contact pillar. A doped layer is then epitaxially grown on the memory stack and bit line is formed on the memory stack. The bit line is self-aligned with the active region.

Abstract: An embodiment device includes a first source/drain region over a semiconductor substrate and a dummy fin adjacent the first source/drain region. The dummy fin comprising: a first portion comprising a first film and a second portion over the first portion, wherein the second portion comprises: a second film; and a third film. The third film is between the first film and the second film, and the third film is made of a different material than the first film and the second film. A width of the second portion is less than a width of the first portion. The device further comprises a gate stack along sidewalls of the dummy fin.

Abstract: A method for preparing a semiconductor structure includes providing a semiconductor substrate having a first surface; disposing a first dielectric layer over the first surface of the semiconductor substrate, a conductive layer over the first dielectric layer, and a second dielectric layer over the conductive layer; disposing a patterned mask over the second dielectric layer; removing portions of the second dielectric layer, the conductive layer and the first dielectric layer exposed through the patterned mask to form a first trench; forming a spacer surrounding the first dielectric layer, the conductive layer and the second dielectric layer; disposing an energy-decomposable mask over the second dielectric layer and the spacer; irradiating a portion of the energy-decomposable mask by an electromagnetic radiation; removing the portion of the energy-decomposable mask irradiated by the electromagnetic radiation; and removing a portion of the second dielectric layer exposed through the energy-decomposable mask.

Abstract: Some embodiments include an integrated assembly having a first deck which has first memory cells, and having a second deck which has second memory cells. The first memory cells have first control gate regions which include a first conductive material vertically between horizontally-extending bars of a second conductive material. The second memory cells have second control gate regions which include a fourth conductive material along an outer surface of a third conductive material. A pillar passes through the first and second decks. The pillar includes a dielectric-barrier material laterally surrounding a channel material. The first and fourth materials are directly against the dielectric-barrier material. Some embodiments include methods of forming integrated assemblies.

Abstract: An array of multi-stack transistor structures is provided, wherein the multi-stack transistor structures are arranged in a plurality of rows and a plurality of columns in the array, wherein each of the multi-stack transistor structures includes two or more vertically arranged transistor stacks, and wherein a dam structure is formed between adjacent two rows in a same column so that a multi-stack transistor structure in one of the adjacent two rows is electrically isolated from a multi-stack transistor structure in the other of the adjacent two rows in the same column.

Abstract: The present disclosure relates generally to doping for conductive features in a semiconductor device. In an example, a structure includes an active region of a transistor. The active region includes a source/drain region, and the source/drain region is defined at least in part by a first dopant having a first dopant concentration. The source/drain region further includes a second dopant with a concentration profile having a consistent concentration from a surface of the source/drain region into a depth of the source/drain region. The consistent concentration is greater than the first dopant concentration. The structure further includes a conductive feature contacting the source/drain region at the surface of the source/drain region.

Abstract: A semiconductor device includes an oxide semiconductor layer including a crystalline region over an insulating surface, a source electrode layer and a drain electrode layer in contact with the oxide semiconductor layer, a gate insulating layer covering the oxide semiconductor layer, the source electrode layer, and the drain electrode layer, and a gate electrode layer over the gate insulating layer in a region overlapping with the crystalline region. The crystalline region includes a crystal whose c-axis is aligned in a direction substantially perpendicular to a surface of the oxide semiconductor layer.

Abstract: In an embodiment, a method includes: stacking a plurality of first dies to form a device stack; revealing testing pads of a topmost die of the device stack; testing the device stack using the testing pads of the topmost die; and after testing the device stack, forming bonding pads in the topmost die, the bonding pads being different from the testing pads.

Abstract: Direct-bonded LED arrays and applications are provided. An example process fabricates a LED structure that includes coplanar electrical contacts for p-type and n-type semiconductors of the LED structure on a flat bonding interface surface of the LED structure. The coplanar electrical contacts of the flat bonding interface surface are direct-bonded to electrical contacts of a driver circuit for the LED structure. In a wafer-level process, micro-LED structures are fabricated on a first wafer, including coplanar electrical contacts for p-type and n-type semiconductors of the LED structures on the flat bonding interface surfaces of the wafer. At least the coplanar electrical contacts of the flat bonding interface are direct-bonded to electrical contacts of CMOS driver circuits on a second wafer.

Abstract: A semiconductor structure includes a substrate and a buried gate structure in the substrate. The buried gate structure includes a gate dielectric layer, a first work function layer, a barrier layer, and a second work function layer. The gate dielectric layer is formed on the sidewalls and the bottom surface of a trench. The work function layer is formed in the trench and contacts the sidewalls and the bottom surface of the gate dielectric layer. The barrier layer is formed on the top surface of the first work function layer. The second work function layer is formed on the barrier layer, and the sidewall of the second work function layer is separated from the gate dielectric layer by a distance. The semiconductor structure further includes an insulating layer in the trench and on the second work function layer.

Abstract: The present disclosure relates to a semiconductor memory device and a method of fabricating the same, and the semiconductor memory device includes a substrate, an active structure and a shallow trench isolation. The active structure is disposed within the substrate and includes a first active region and a second active region. The first active region includes a plurality of active region units, and the second active region is disposed at an outer side of the first active region to directly connect to a portion of the active region units. The second active region includes a plurality of first openings disposed an edge of the second active region. The shallow trench isolation is disposed within the substrate, to surround the active structure.

Abstract: A semiconductor structure including a semiconductor substrate and at least one patterned dielectric layer is provided. The semiconductor substrate includes a semiconductor portion, at least one first device, at least one second device and at least one first dummy ring. The at least one first device is disposed on a first region surrounded by the semiconductor portion. The at least one second device and the at least one first dummy ring are disposed on a second region, and the second region surrounds the first region. The at least one patterned dielectric layer covers the semiconductor substrate.