Abstract: A sensor device includes a first substrate of semiconductor material having opposing first and second surfaces, photodetectors configured to receive light impinging on the first surface, and first contact pads each exposed at both the first and second surfaces and electrically coupled to at least one of the photodetectors. A second substrate comprises opposing first and second surfaces, electrical circuits, a second contact pads each disposed at the first surface of the second substrate and electrically coupled to at least one of the electrical circuits, and a plurality of cooling channels formed as first trenches extending into the second surface of the second substrate but not reaching the first surface of the second substrate. The first substrate second surface is mounted to the second substrate first surface such that each of the first contact pads is electrically coupled to at least one of the second contact pads.

Abstract: A method of making a stacked chip layout includes placing a first active circuit block over a central processing chip having a first area, the first active circuit block having a second area less than the first area. The method further includes placing a second active circuit block over the first active circuit block, the second active circuit block having a third area less than the first area, wherein the second active circuit block partially overlaps the first active circuit block and exposes a portion of the first active circuit block. The method further includes placing a third active circuit block over the second active circuit block wherein the third active circuit block partially overlaps at least one of the first active circuit block or the second active circuit block, and the third active circuit block exposes at least a portion of the first and second active circuit blocks.

Abstract: A method includes forming a multilayered stack on a surface of a supporting layer. The multilayered stack is composed of alternating layers of compressively strained Silicon Germanium (Si1-xGex) and tensily strained Carbon-doped Silicon (Si:C). The method further includes etching the multilayered stack to form at least one Fin precursor structure and annealing the Fin precursor structure to remove Carbon from the strained Si:C layers to form Carbon-depleted layers and to diffuse Germanium from the Si1-xGex layers into the Carbon-depleted layers producing a Si1-xGex Fin. A structure that is disclosed includes a Semiconductor on Insulator (SOI) layer disposed on a layer of buried oxide and a multilayered stack on a surface of the SOI layer. The multilayered stack is composed of alternating layers of compressively strained Si1-xGex and tensily strained Si:C. The structure further includes a hardmask layer disposed on a top surface of the multilayered stack.

Abstract: A light emitting diode (LED) chip including a first type semiconductor layer, an light-emitting layer, a second type semiconductor layer, a current blocking layer, a transparent conductive layer and an electrode is provided. The light-emitting layer is disposed on the first type semiconductor layer. The second type semiconductor layer is disposed on the light-emitting layer. The current blocking layer is disposed on the second type semiconductor layer. The transparent conductive layer is disposed on the second type semiconductor layer and covered the current blocking layer. The electrode is disposed on the transparent conductive layer corresponding to the current blocking layer. The current blocking layer and the electrode respectively have a first width and a second width in a cross section view, and the first width of the current blocking layer is larger than the second width of the electrode.

Abstract: A memory device includes a memory cell on a first region of a substrate. An active region is in a second region neighboring the first region of the substrate, and an extension direction of the active region has an acute angle with the <110> direction of the substrate. A transistor serving as a peripheral circuit is on the second region of the substrate. In the memory device, defects or failures due to a crystal defects or a dislocation of the substrate may decrease.

Abstract: According to one embodiment, a semiconductor device is disclosed. The device includes a foundation layer including first and second layers being different from each other in material, and the foundation layer including a surface on which a boundary of the first and second layers is presented, a catalyst layer on the surface of the foundation layer, and the catalyst layer including a protruding area. The device further includes a graphene layer being in contact with the protruding area.

Abstract: A method includes forming a multi-stacked electronic device having two or more electronic components, each of the electronic components includes a leadframe, the leadframes of each electronic component are physically joined together using a non-solder metal joining process to form a joint, and the joint is located outside a solder connection region.

Abstract: A trench-isolated RESURF diode structure (100) is provided which includes a substrate (150) in which is formed anode (130, 132) and cathode (131) contact regions separated from one another by a shallow trench isolation region (114, 115), along with a non-uniform cathode region (104) and peripheral anode regions (106, 107) which define vertical and horizontal p-n junctions under the anode contact regions (130, 132), including a horizontal cathode/anode junction that is shielded by the heavily doped anode contact region (132).

Abstract: A low noise infrared photodetector has an epitaxial heterostructure that includes a photodiode and a transistor. The photodiode includes a high sensitivity narrow bandgap photodetector layer of first conductivity type, and a collection well of second conductivity type in contact with the photodetector layer. The transistor includes the collection well, a transfer well of second conductivity type that is spaced from the collection well and the photodetector layer, and a region of first conductivity type between the collection and transfer wells. The collection well and the transfer well are of different depths, and are formed by a single diffusion.

Abstract: Provided is a light-emitting element having a light-emitting layer which contains at least a host material and a plurality of guest materials, where the host material has a lower T1 level than that of at least one of the plurality of guest materials. The emission of the one of the plurality of guest materials exhibits a multicomponent decay curve, and the lifetime thereof is less than or equal to 15 ?sec, preferably less than or equal to 10 ?sec, more preferably less than or equal to 5 ?sec, where the lifetime is defined as a time for the emission to decrease in intensity to 1/100 of its initial intensity.

Abstract: A method for manufacturing a light emitting device, having; a die bonding step of mounting a light emitting element on a board; a phosphor layer formation step of forming a phosphor layer that contains a phosphor by spraying on surfaces of the board and the light emitting element after the die bonding step; and a cover layer formation step of forming a cover layer that contains at least one type of light reflecting material and light blocking material on a surface of the phosphor layer over the board.

Abstract: The present invention provides an encapsulant with a base for use in semiconductor encapsulation, for collectively encapsulating a device mounting surface of a substrate on which semiconductor devices are mounted, or a device forming surface of a wafer on which semiconductor devices are formed, the encapsulant comprising the base, an encapsulating resin layer composed of an uncured or semi-cured thermosetting resin formed on one surface of the base, and a surface resin layer formed on the other surface of the base. The encapsulant enables a semiconductor apparatus having a good appearance and laser marking property to be manufactured.

Abstract: Provided is a substrate for mounting an LED element in which a stable light-emitting surface is obtained, as well as a light source and an LED display using this substrate, so that the axis at which light is emitted by a chip LED does not vary. The substrate for mounting an LED element (1) comprises a substrate (1a) on which an LED element can be mounted, and a wiring layer (2) for supplying electricity to an LED element (7). The wiring layer (2) for supplying electricity to the LED element (7) is formed on a mirror-finished surface on the entirety of a substrate surface on which the LED element is mounted, except for an insulating space 4 capable of providing insulation between terminals of the LED element.

Abstract: In a field effect transistor, a carbon concentration in a buffer layer at the side closer to a high resistance layer is not less than 0.8×1019/cm3 and not more than 1.0×1021/cm3, a carbon concentration in the high resistance layer at the side closer to the buffer layer is not less than 3.7×1018/cm3 and not more than 1.0×1021/cm3, and a carbon concentration in the high resistance layer at the side closer to the channel layer is not less than 1.4×1019/cm3 and not more than 1.0×1021/cm3.

Abstract: According to an embodiment of the present invention, a chip package is provided. The chip package includes: a patterned conducting plate having a plurality of conducting sections electrically separated from each other; a plurality of conducting pads disposed on an upper surface of the patterned conducting plate; a chip disposed on the conducting pads; a plurality of conducting bumps disposed on a lower surface of the patterned conducting plate, wherein each of the conducting bumps is electrically connected to a corresponding one of the conducting sections of the patterned conducting plate; and an insulating support layer partially surrounding the conducting bumps.

Abstract: A non-volatile memory device includes a charge trapping layer for trapping charges. The charge trapping layer includes a linker layer formed over a substrate and including linkers to be bonded to metal ions metallic nanoparticles formed out of the metal ions over the linker layer and a nitride filling gaps between the metallic nanoparticles.

Abstract: A non-volatile memory device includes a floating gate for charging and discharging of charges over a substrate. The floating gate comprises a linker layer formed over the substrate and including linkers to be bonded to metal ions and metallic nanoparticles formed out of the metal ions over the linker layer.

Abstract: A semiconductor device with a buried layer has a deep trench structure abutting the buried layer and a self-aligned sinker along sidewalls of the deep trench structure. The semiconductor device may be formed by forming a portion of a deep trench down to the buried layer, and implanting dopants into a substrate of the semiconductor device along sidewalls of the deep trench, and subsequently forming a remainder of the deep trench extending below the buried layer. Alternatively, the semiconductor device may be formed by forming the deep trench to extend below the buried layer, and subsequently implanting dopants into the substrate of the semiconductor device along sidewalls of the deep trench.

Abstract: A solder bump support structure and method of manufacturing thereof is provided. The solder bump support structure includes an inter-level dielectric (ILD) layer formed over a silicon substrate. The ILD layer has a plurality of conductive vias. The structure further includes a first insulation layer formed on the ILD layer. The solder bump support structure further includes a pedestal member formed on the ILD layer which includes a conductive material formed above the plurality of conductive vias in the ILD layer coaxially surrounded by a second insulation layer. The second insulation layer is thicker than the first insulation layer. The structure further includes a capping under bump metal (UBM) layer formed over, and in electrical contact with, the conductive material and formed over at least a portion of the second insulation layer of the pedestal member.

Abstract: A circuit arrangement includes a substrate, an integrated circuit (IC) component attached to the substrate, and one or more round wire segments attached to the substrate. The one or more round wire segments have first and second portions for connecting to the IC component, and each first and second portion has a planar landing area extending longitudinally along the wire. The circuit arrangement further includes bond wires connecting the landing areas to the IC component.