Abstract: Techniques are disclosed for identifying fixed bits of a bitstring format. One or more processors are configured to generate a first bitstring having respective first bit values that have a first satisfiability state and generate a second bitstring having respective second bit values that have a second satisfiability state. The one or more processors are configured to identify first potential free bits having respective first common values and generate a third bitstring having first potential free bits with the respective first common values and third remaining bits. The one or more processors are configured to identify second potential free bits having respective second common values and identify a fixed bit that is not included in the first potential free bits and is not included in the second potential free bits.

Abstract: An electrically conductive material configured having at least one opening of various unlimited geometries extending through its thickness is provided. The opening is designed to modify eddy currents that form within the surface of the material from interaction with magnetic fields that allow for wireless energy transfer therethrough. The opening may be configured as a cut-out, a slit or combination thereof that extends through the thickness of the electrically conductive material. The electrically conductive material is configured with the cut-out and/or slit pattern positioned adjacent to an antenna configured to receive or transmit electrical energy wirelessly through near-field magnetic coupling (NFMC). A magnetic field shielding material, such as a ferrite, may also be positioned adjacent to the antenna. Such magnetic shielding materials may be used to strategically block eddy currents from electrical components and circuitry located within a device.

Abstract: Technologies are provided for time-to-digital conversion without reliance on a clocking signal. The technologies include a clockless TDC apparatus that can map continuous pulse-widths to binary bits represented via an iterative chaotic map (e.g., tent map, Bernoulli shift map, or similar). The clockless TDC apparatus can convert separated pulses to a single asynchronous digital pulse that turns on when a sensor detects a first pulse and turns off when the sensor detects a second pulse. The asynchronous digital pulse can be iteratively stretched and folded in time according to the chaotic map. The clockless TDC can generate a binary sequence that represents symbolic dynamics of the chaotic map. The process can be implemented by using an iterative time delay component until a precision of the binary output is either satisfied or overwhelmed by noise or other structural fluctuations of the TDC apparatus.

Abstract: A digital-to-analog converter includes an array of capacitors, an array of capacitor switches, positive and negative high-bandwidth reference buffers, positive and negative low-bandwidth reference buffers, and a reference-voltage-selection switch. Each capacitor switch electrically couples a respective capacitor to either a positive or a negative reference voltage line. The reference-voltage-selection switch electrically couples the positive and negative reference voltage lines to either positive and negative high-bandwidth voltages or to positive and negative low-bandwidth voltages. The positive and negative high-bandwidth voltages are produced by the positive and negative high-bandwidth reference buffers. The positive and negative low-bandwidth voltages are produced by the positive and negative low-bandwidth reference buffers.

Abstract: In various embodiments, an encoded sequence (e.g., a compressed sequence for uncompressed data) that includes variable-length codes is decoded in an iterative fashion to generate a decoded sequence of symbols. During each iteration, a group of threads decode in parallel the codes in the encoded sequence to generate symbols. The group of threads then compute offsets based on the sizes of the symbols. Subsequently, the group of threads generates in parallel a contiguous portion of the decoded sequence based on the symbols, an output address, and the offsets.

Abstract: An antenna system includes: a ground conductor; a substrate; a pair of planar dipole conductors disposed such that at least a portion of the substrate is disposed between the ground conductor and the pair of dipole conductors; a pair of energy couplers each electrically connected to a respective one of the pair of dipole conductors; and a pair of isolated lobes including electrically-conductive material. The pair of isolated lobes are electrically separate from the pair of dipole conductors and the pair of energy couplers, and disposed between the pair of dipole conductors and the ground conductor.

Abstract: A signal analyzer for analyzing a signal includes a frontend with at least two interleaved digitizers configured to digitize an input signal, thereby generating a digitized input signal. The signal analyzer also includes a first interleave alignment filter established by a hardware interleave alignment filter that is configured to hardware-compensate non-ideal effects of the frontend in the digitized input signal in real-time, thereby generating a hardware-compensated, digitized input signal. Further, the signal analyzer includes an acquisition memory configured to store the hardware-compensated, digitized input signal, thereby acquiring an acquired signal. Moreover, the signal analyzer includes a second interleave alignment filter configured to fine-compensate further non-ideal effects of the frontend in a post-processing of the acquired signal.

Abstract: A system comprises an encoder configured to entropy encode a bitstream comprising both compressible and non-compressible symbols. The encoder parses the bitstream into a compressible symbol sub-stream and a non-compressible sub-stream. The non-compressible symbol sub-stream bypass an entropy encoding component of the encoder while the compressible symbol sub-stream is entropy encoded. When a quantity of bytes of entropy encoded symbols and bypass symbols is accumulated a chunk of fixed or known size is formed using the accumulated entropy encoded symbol bytes and the bypass bytes without waiting on the full bitstream to be processed by the encoder. In a complementary manner, a decoder reconstructs the bitstream from the packets or chunks.

Abstract: A DAC cell includes first and second transistors, drain-source coupled at a first node, a gate of the second transistor coupled to a data input (D), and third and fourth transistors, drain-source coupled at a second node, a gate of the fourth transistor coupled to a complement of the data input (DB). The circuit further includes first and second shadow transistors each coupled between the first node and ground, a gate of the first shadow transistor coupled to a switching input (S) and a gate of the second shadow transistor coupled to a complement of the switching input (SB). The circuit still further includes third and fourth shadow transistors each coupled between the second node and ground, a gate of the third shadow transistor coupled to S and a gate of the fourth shadow transistor coupled to SB.

Abstract: A gain stage, such as an amplifier, e.g., an instrumentation amplifier, can receive an input signal and adjust the level of the input signal, e.g., amplify or attenuate. An output voltage of the gain stage can be applied to a subsequent circuit. Using various techniques, a second stage of an instrumentation amplifier, which can include a transconductance stage that converts a current to a voltage that can be applied to an output node of the instrumentation amplifier, can be removed. Removal of such a second stage can allow an output current from the gain stage to be applied directly from a current output node to an input node of a subsequent circuit.

Abstract: A component carrier has a laminated stack including at least one electrically conductive layer structure and/or at least one electrically insulating layer structure, a front-end chip on and/or in the stack and extending at least up to a main surface of the stack, an antenna interface on an opposing other main surface of the stack, and an impedance matching circuitry in the stack and arranged vertically between the front-end chip and the antenna interface.

Abstract: A system for converting a voltage into output codes includes logic gates for processing delay signals based on earlier and later arriving signals generated by preamplifiers, delay comparators for generating digital signals representative of most significant bits of respective codes, and for transmitting delay residue signals representative of less significant bits of the codes, and an auxiliary delay comparator for generating an auxiliary digital signal for use in generating the output codes. A system may include logic gates for generating delay signals based on earlier and later arriving signals, delay comparators for generating digital signals representative of most significant bits of respective codes, and for transmitting delay residue signals representative of less significant bits, and a multiplexer system for transmitting a selected one of the residue signals.

Abstract: A method and apparatus for encoding and decoding of floating-point number is provided. The method for encoding is used to convert at least one original floating-point number to at least one encoded floating-point number. The method for encoding includes: determining a number of exponent bits of the at least one encoded floating-point number and calculating an exponent bias according to at least one original exponent value of the at least one original floating-point number; and converting an original exponent value of a current original floating-point number of the at least one original floating-point number to an encoded exponent value of a current encoded floating-point number of the at least one encoded floating-point number according to the exponent bias.

Abstract: A system including a circuit, including a first preamplifier, a sampling switch, a regenerative latch, and a second preamplifier aligned in a pipelined sequence with the first preamplifier, wherein the first and second preamplifier are associated with dynamic comparator and configured to gain signal utilizing multiple cascaded gains and sample-and-hold stages including a plurality of phases.

Abstract: A digital signal generation assumes that a base frequency (the frequency with which the primitive phase angles are specified relative to) is equal to the carrier frequency for all relevant times. But this causes errors in the digital signals output to each array element transducer. Thus, it is necessary for the development of a signal generation system that is capable of producing a digital signal using the free selection of amplitude and phase. This is used to produce a substantially error-free signal that preserves the amplitude and phase relative to a constant base frequency while allowing the carrier frequency to vary.

Abstract: Embodiments of the present disclosure provide an apparatus including: a phase detector for detecting a write frequency of a deserializer and a read frequency of a serializer, such that the phase detector outputs a first code sequence in response to the write frequency being greater than the read frequency, or a second code sequence at the rotator input in response to the write frequency being less than the read frequency; and a phase rotator for receiving the first code sequence or the second code sequence from the phase rotator to transmit a pacing signal having the read frequency to the deserializer, wherein the pacing signal causes the read frequency to increase or decrease based on whether the read frequency is different from the write frequency.

Abstract: An example radio frequency (RF) front-end module may include a printed circuit board (PCB) including a ground plane, an RF integrated circuit (RFIC) including RF components mounted on the PCB, and an antenna array on the PCB. The antenna array may operate at a first resonant frequency in a wireless communication network. Further, the RF front-end module may include a slot defined in the ground plane to provide a second resonant frequency in the wireless communication network. The second resonant frequency is lower than the first resonant frequency.

Abstract: A method of encoding data values where the data values are arranged into words, each word having a plurality of input values and one or more padding bits. A word is encoded by determining whether more than half of the bits in a portion of the word are ones, where the portion may be some or all of the bits of the input values in the word, and in response to determining that more than half of the bits in the portion are ones, inverting all the bits in the portion and setting a corresponding padding bit to a value to indicate the inversion.

Abstract: A converter circuit includes an analog-to-digital signal conversion path. An input port receives an analog input signal having an offset, and an output port delivers a digital output signal quantized over M levels. The digital output signal is sensed by a digital-to-analog feedback path, which includes a digital-to-analog converter applying to the input port an analog feedback signal produced as a function of an M-bit digital word under control of a two-state signal having alternating first and second states. M-bit digital word generation circuitry coupled to the digital-to-analog converter and sensitive to the two-state signal produces, alternately, during the first states, a first M-bit digital word, which is a function of the digital output signal quantized over M levels, and, during the second states, a second M-bit digital word, which is a function a correction value of the offset in the analog input signal.

Abstract: Techniques are provided for implementing additional compression for existing compressed data. Format information stored within a data block is evaluated to determine whether the data block is compressed or uncompressed. In response to the data block being compressed according to a first compression format, the data block is decompressed using the format information. The data block is compressed with one or more other data blocks to create compressed data having a second compression format different than the first compression format.