Abstract: A voltage generator including an oscillator having an output, a charge pump having an input and an output, the input of the charge pump being coupled to the output of the oscillator, a smoothing capacitor, a resistor having an input end and an output end, wherein the input end is coupled to the charge pump and the output end is coupled to the smoothing capacitor, and a shorting element connected in parallel with the resistor and which, when turned on, causes the resistor to be at least partially bypassed, wherein the voltage generator is configured to supply voltage to a radio frequency (RF) switch via the smoothing capacitor, and a frequency of the oscillator is controlled to be faster during a switching period of the RF switch.

Abstract: According to one embodiment, an apparatus is for use with a remote circuit. The apparatus has a first input for receiving an input voltage, a second input for receiving a power supply voltage, and a third input for receiving an input clock having a high state corresponding to the power supply voltage and a low state corresponding to a return for the power supply voltage. The apparatus includes a first shift circuit coupled to the first input and the third input, and configured to output a first output clock, the first output clock having a low state corresponding to the input voltage. The apparatus further includes a second shift circuit coupled to the first input and the first shift circuit, and configured to output a second output clock, the second output clock having a high state corresponding to the input voltage.

Abstract: A substrate bias circuit and method for biasing a substrate are provided. A substrate bias circuit includes a first voltage source, a second voltage source, a diode coupled between the first voltage source and the second voltage source, and a plurality of transistors, each transistor in the plurality of transistors having a substrate terminal. In one example, the first voltage source supplies, via the diode, the substrate terminal of a first transistor of the plurality of transistors during a power-up, and the second voltage source supplies the substrate terminal of the first transistor after the power-up.

Abstract: The present disclosure relates to a Zener diode including a cathode region having a first conductivity type, formed on a surface of a semiconductor substrate having a second conductivity type. The Zener diode includes an anode region having the second conductivity type, formed beneath the cathode region. One or more trench isolations isolate the cathode and anode regions from a remainder of the substrate. A first conducting region is configured to, when subjected to an adequate voltage, generate a first electric field perpendicular to an interface between the cathode and anode regions. A second conducting region is configured to, when subjected to an adequate voltage, generate a second electric field parallel to the interface between the cathode and anode regions.

Abstract: The present disclosure relates to a Zener diode including a Zener diode junction formed in a semiconductor substrate along a plane parallel to the surface of the substrate, and positioned between a an anode region having a first conductivity type and a cathode region having a second conductivity type, the cathode region extending from the surface of the substrate. A first conducting region is configured to generate a first electric field perpendicular to the plane of the Zener diode junction upon application of a first voltage to the first conducting region, and a second conducting region is configured to generate a second electric field along the plane of the Zener diode junction upon application of a second voltage to the second conducting region.

Abstract: An initialization device for a charge pump includes a driving circuit and a bias voltage circuit. The driving circuit is between two power supply nodes. The driving circuit includes a first node configured to be coupled to an output electrode of a capacitor in the charge pump. The bias voltage circuit is coupled to the two power supply nodes. The bias voltage circuit includes a second node coupled to a control terminal of the driving circuit. In response to an applied initialization signal, the bias voltage circuit is configured to output a bias voltage to the second node. The bias voltage has at least two levels that correspond to levels of the applied initialization signal. In response to the bias voltage, the driving circuit is configured to output an output signal having at least two levels that correspond to the at least two levels of the bias voltage.

Abstract: A semiconductor system includes a master chip and a plurality of slave chips. The master chip controls internal voltage levels of the respective slave chips based on signals outputted from the plurality of slave chips such that, by referring to any one slave chip of the plurality of slave chips, internal voltage levels of remaining slave chips are controlled.

Abstract: In a reference signal distribution system, a first subsystem is configured to distribute a reference signal to a second subsystem. The first subsystem includes multiple diode-connected devices biased by a reference current and configured to establish a differential voltage between a first node and a second node. The second subsystem includes multiple diode-connected devices driven by the differential voltage and configured to generate a copy current associated with the reference current.

Abstract: A semiconductor device includes a first power source line which accepts the supply of power in the active mode, a second power source line which accepts the supply of power in the active mode and the standby mode, a memory circuit to be coupled with the first and second power source lines and a first switch which electrically couples the first power source line with the second power source line in the active mode and electrically decouples the first power source line from the second power source line in the standby mode. The memory circuit includes a memory array, a peripheral circuit and a second switch. Each of the first and second switches includes a first PMOS transistor and a second PMOS transistor.

Abstract: There is provided a current mirror that includes at least one bias amplifier configured to adjust a gate line voltage by feeding currents to the gate line to make constant gate-source voltages of a plurality of FETs (Field Effect Transistors), the gate line connecting gates of the FETs each being a load component in the current mirror.

Abstract: A circuit that includes a first diode-connected dummy device, a second diode-connected dummy device, a third diode-connected dummy device, a fourth diode-connected dummy device, and a first discharge path. The second diode-connected dummy device connected in cascode with the first diode-connected dummy device. The fourth diode-connected dummy device connected in cascode with the third diode-connected dummy device. The first and the second diode-connected dummy devices are formed in a first region. The third and the fourth diode-connected dummy devices are formed in a second region which is outside the first region. The first discharge path configured to discharge charges from at least one of the first and the second diode-connected dummy devices in the first region to a reference voltage terminal of one of the third and the fourth diode-connected dummy devices in the second region.

Abstract: A low voltage ripple charge pump with slew rate control includes a frequency divider, a clock generator, a current mirror, a switching circuit, a diode network, two capacitors, and a comparator. The frequency divider generates a clock signal from an oscillating signal. The clock generator generates first and second clock signals from the clock signal. The current mirror generates first and second current signals using a reference current. The switching circuit generates first and second voltage signals using the first and second clock signals and the first and second current signals. The comparator generates the oscillating signal based on the first and second voltage signals. The capacitors receive the voltage signals and are connected to the diode network for generating an output signal. The charge pump has low output voltage ripple with small filtering capacitance, which is achieved via slew rate control.

Abstract: A temperature sensor circuit includes: an output circuit including a first field-effect transistor configured to output a current proportional to temperature when a voltage twice as high as a threshold voltage is applied to a gate of the first field-effect transistor; and a voltage generating circuit configured to generate the voltage twice as high as the threshold voltage by a plurality of field-effect transistors and supply the generated voltage twice as high as the threshold voltage to the gate of the first field-effect transistor.

Abstract: An interface supply circuit includes a power supply unit, a control unit coupled to the power supply unit, and a detection unit coupled to the control unit. The detection unit is configured to couple to an interface. The detection unit is configured to output a first control signal upon detecting that a device is inserted into the interface and output a second control signal upon detecting that no device is inserted into the interface. The control unit is configured to be switched on upon receiving the first control signal. The power supply unit is configured to supply power to the interface in event that the control unit is switched on. The power supply unit is configured to be disconnected from the interface in event that the control unit receives the second control signal.

Abstract: Embodiments of the invention provide low-noise arrangements for very-large-scale integration (VLSI) differential input/output (I/O) structures (I/O pins, solder bumps, vias, etc.). Novel geometries are described for arranging differential pairs of I/O structures in perpendicular or near-perpendicular “quads.” The geometries effectively place one differential pair on or near the perpendicular bisector of its adjacent differential pair, such that field cancellation and differential reception can substantially eliminate noise without the need for added spacing or shields. By exploiting these effects, embodiments can suppress noise, independent of I/O structure spacing, and arbitrarily small spacings are permitted. Such arrangements can be extended into running chains, and even further into arrays of parallel chains. The parallel chains can be separated by supply structures (e.g.

Abstract: The invention relates to a retrofit LED lamp having an LED module, a driver circuit for supplying power to the LED module, a base for making mechanical and electrical contact with a bulb fitting and a heat sink arrangement for dissipating the heat produced during operation at the LED module and/or the driver circuit. The heat sink arrangement in this case has a metal mount insert consisting of a mount plate with an integrally attached collar, the mount plate bearing, in thermally conductive contact, the LED module, and a transparent upper shell being fitted to the collar of the mount insert in the light exit direction and a thermally conductive lower shell being fitted, in areal contact, in the direction of the base for heat dissipation, said upper shell and said lower shell together forming a housing of the LED lamp which surrounds the LED module and the mount insert.

Abstract: A semiconductor device according to an embodiment comprises a first transistor capable of supplying or interrupting power to a load. A clamper comprises a first clamping part and a second clamping part connected in series between one end of the first transistor and a gate of the first transistor and becomes a conduction state when a voltage of the one end of the first transistor exceeds a predetermined voltage. A clamp operation detector is provided between the first clamping part and the second clamping part. A second transistor is connected in parallel with the second clamping part. A delay circuit is provided between the clamp operation detector and a gate of the second transistor.

Abstract: A voltage charge pump circuit with boost capacitor segments and boost delay chain structures are provided. The voltage charge pump circuit comprising a plurality of boost capacitor segments each of which is individually controlled by a respective signal line of a boost delay chain structure.

Abstract: A semiconductor integrated circuit includes a control unit that controls power supply to a plurality of power supply domains respectively corresponding to a plurality of functions included in an apparatus. A circuit integrates bus signals between the plurality of power supply domains is included in a specific power supply domain out of the plurality of power supply domains, and the control unit controls the power supply to the specific power supply domain to be performed prior to the other power supply domains connected with the specific power supply domain.

Abstract: A MOS device includes first and second sets of power rails. The first set of power rails extends across the MOS device and includes at least two power rails for providing a first voltage to the MOS device. The first set of power rails is interior to an edge of a cell boundary in the MOS device. At least one power rail of the first set of power rails extends over a pMOS active region of the MOS device. The second set of power rails extends across the MOS device and includes at least two power rails for providing a second voltage to the MOS device. The second set of power rails is interior to an edge of the cell boundary in the MOS device. At least one power rail of the second set of power rails extends over an nMOS active region of the MOS device.