Patents Examined by Jeffrey Zweizig
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Patent number: 9503074Abstract: In some method and apparatus embodiments, an RF circuit comprises a switch transistor having a source, a drain, a gate, and a body. A gate control voltage is applied to the gate of the switch transistor. A body control voltage is applied to the body of the switch transistor. The body control voltage is a positive bias voltage when the switch transistor is in an on state. In some embodiments, an RF circuit comprises a control voltage applied to the gate of the switch transistor through a first resistance and applied to the body of the switch transistor through a second resistance. The first resistance is different from the second resistance.Type: GrantFiled: March 6, 2015Date of Patent: November 22, 2016Assignee: Qualcomm IncorporatedInventors: Max Samuel Aubain, Clint Kemerling
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Patent number: 9503088Abstract: The invention provides a method for recovering NBTI/PBTI related parameter degradation in MOSFET devices. The method includes operating the at least one MOSFET device in a standby mode, exiting the at least one MOSFET device from the standby mode, holding the at least one MOSFET device in an active state for a predetermined time span after exiting the standby mode, and operating the at least one MOSFET device in an operational mode after the predetermined time span has elapsed.Type: GrantFiled: January 10, 2013Date of Patent: November 22, 2016Assignee: FREESCALE SEMICONDUCTOR, INC.Inventors: Sergey Sofer, Michael Priel, Noam Sivan
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Patent number: 9503063Abstract: A system for adjusting qubit frequency includes a qubit device having a Josephson junction and a shunt capacitor coupled to electrodes of the Josephson junction. A cantilevered conductor is separated from the shunt capacitor by a spacing. An adjustment mechanism is configured to deflect the cantilevered conductor to tune a qubit frequency for the qubit device.Type: GrantFiled: September 16, 2015Date of Patent: November 22, 2016Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: David W. Abraham, Jerry M. Chow, Jay M. Gambetta, John A. Smolin
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Patent number: 9503055Abstract: A signal processing apparatus that includes a circuit in which a signal processing function is performed during a first time period, the signal processing apparatus including or being associated with a switch or a filter in a power supply to the signal processing apparatus so as to disconnect the signal processing apparatus from the power supply or to filter the power supply during a second time period that is coincident with at least part of the first time period.Type: GrantFiled: March 9, 2015Date of Patent: November 22, 2016Assignee: Analog Devices GlobalInventors: Patrick J. Meehan, Mark T. Kelly, Christopher Peter Hurrell, Thomas Anthony Conway, Donal O'Sullivan, Michael Hennessy, William Hunt
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Patent number: 9501078Abstract: In a bandgap voltage reference with low package shift, a proportional to absolute temperature (PTAT) voltage is generated using a single diode biased at two different current levels at two different times. Using the same diode for both current density measurements removes the absolute value of the base-emitter junction voltage (Vbe) and any package shift in the PTAT voltage. The bandgap voltage reference can be implemented in a single or differential circuit topology. In some implementations, the bandgap voltage reference can include circuitry for curvature correction.Type: GrantFiled: April 20, 2015Date of Patent: November 22, 2016Assignee: Atmel CorporationInventors: Danut Manea, Jeff Kotowski, Scott N. Fritz, Yongliang Wang
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Patent number: 9490244Abstract: An integrated circuit comprises a load transistor including first and second load terminals and a load control terminal. The integrated circuit further comprises a clamping structure. The clamping structure comprises a clamping transistor, the clamping transistor including first and second clamping transistor load terminals and a gate terminal. The clamping transistor is electrically coupled between the load control terminal and the first load terminal and a clamping voltage of the load transistor is determined by a threshold voltage Vth of the clamping transistor.Type: GrantFiled: May 8, 2015Date of Patent: November 8, 2016Assignee: Infineon Technologies Austria AGInventors: Jens Barrenscheen, Anton Mauder
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Patent number: 9484892Abstract: An integrated circuit compensates for circuit aging by measuring the aging with an aging sensor and controlling a supply voltage based on the measured aging. The operating environment for the aging sensor can be set to reduce impacts of non-aging effects on the measured aging. For example, the operating environment can use a temperature inversion voltage. An initial aging measurement value which is the difference between an initial aged measurement and an initial unaged measurement can be stored on the integrated circuit. A core power reduction controller can use the measured aging and the stored initial aging measurement value to update a performance-sensor target value and then perform adaptive voltage scaling using the using the updated performance-sensor target value.Type: GrantFiled: September 10, 2015Date of Patent: November 1, 2016Assignee: QUALCOMM IncorporatedInventors: Mohammad Reza Kakoee, Shih-Hsin Jason Hu, Min Chen, Jasmin Smaila Ibrahimovic, Carlos Auyon, Sorin Adrian Dobre, Navid Toosizadeh, Nan Chen, Mohamed Waleed Allam
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Patent number: 9484927Abstract: A semiconductor device includes a semiconductor element having a gate and controlled with a gate voltage, a gate drive circuit which controls the gate voltage, an electrode connected to the semiconductor element, a principal current in the semiconductor element flowing through the electrode, a temperature sensing part which senses the temperature of the electrode, a generation section which generates, on the basis of the temperature sensed by the temperature sensing part, a first control signal for giving a maximum amount of energization to the semiconductor element in such a range that the temperature of the electrode does not exceed a predetermined temperature, and a comparison section which compares the first control signal and a second control signal transmitted from the outside for the purpose of controlling the gate voltage, and selects a selective control signal which is one of the control signals with which the temperature of the electrode can be limited.Type: GrantFiled: December 28, 2012Date of Patent: November 1, 2016Assignee: Mitsubishi Electric CorporationInventors: Mitsunori Aiko, Shintaro Araki
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Patent number: 9478469Abstract: Among other things, an integrated circuit and method for routing electrical pathways of an integrated circuit is provided. The integrated circuit comprises a buffer chain coupling a first cell of the integrated circuit to a second cell of the integrated circuit. An electrical pathway coupling a first inverter of the buffer chain with a second inverter of the buffer chain extends through a first set of metal layers and is routed to form a pulse-like shape having an apex at a top layer of the first set.Type: GrantFiled: March 16, 2015Date of Patent: October 25, 2016Assignee: Taiwan Semiconductor Manufacturing Company LimitedInventors: Yi-Lin Chuang, Chien-Hui Chen, Wei-Pin Changchien, Chin-Her Chien, Nan-Hsin Tseng
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Patent number: 9472246Abstract: An integrated circuit includes an input/output “I/O” cell arranged to drive an output signal and an activity analysis unit arranged to generate an activity factor based on the output signal. The activity factor represents a switching activity intensity of the I/O cell. The switching activity intensity is associated with an ageing effect of the I/O cell. The circuit further includes a calibration unit arranged to generate a switching pattern signal based on the generated activity factor and an I/O calibration cell arranged to be driven by the switching pattern signal, wherein the switching pattern signal emulates the ageing effect of the I/O cell.Type: GrantFiled: November 7, 2012Date of Patent: October 18, 2016Assignee: FREESCALE SEMICONDUCTOR, INC.Inventors: Michael Priel, Dan Kuzmin, Sergey Sofer
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Patent number: 9466555Abstract: A semiconductor may include a core block configured to store and output data, and may be configured to output internal information. The semiconductor may include a through via configured for signal transfer with another semiconductor chip. The semiconductor may include an internal information processing circuit configured to transmit internal information selected from the internal information to the through via, or may be configured to output internal information of the other semiconductor chip, which has been transmitted through the through via, to an exterior through a special purpose pin, in response to test signals.Type: GrantFiled: February 18, 2015Date of Patent: October 11, 2016Assignee: SK HYNIX INC.Inventors: Jae Seung Lee, Byung Kuk Yoon
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Patent number: 9455718Abstract: A semiconductor device includes a semiconductor element having a gate and controlled with a gate voltage, a gate drive circuit which controls the gate voltage, an electrode connected to the semiconductor element, a principal current in the semiconductor element flowing through the electrode, a temperature sensing part which senses the temperature of the electrode, a generation section which generates, on the basis of the temperature sensed by the temperature sensing part, a first control signal for giving a maximum amount of energization to the semiconductor element in such a range that the temperature of the electrode does not exceed a predetermined temperature, and a comparison section which compares the first control signal and a second control signal transmitted from the outside for the purpose of controlling the gate voltage, and selects a selective control signal which is one of the control signals with which the temperature of the electrode can be limited.Type: GrantFiled: December 28, 2012Date of Patent: September 27, 2016Assignee: Mitsubishi Electric CorporationInventors: Mitsunori Aiko, Shintaro Araki
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Patent number: 9448578Abstract: An interface supply circuit includes a power supply unit, a first and a second control circuit, and a detection unit coupled to an interface. The detection unit is configured to output a first control signal upon detecting a corresponding device is inserted into the interface and output a second control signal upon detecting no device is inserted into the interface. The first control circuit is configured to switch off in event receiving the first control signal and switch on in event receiving the second control signal. The second control circuit is configured to switch on in event the first control circuit is switched off and switch off in event the first control circuit is switched on. The power supply unit is configured to supply power to the interface after the second control circuit is switched on and be disconnected from the interface after the second control circuit is switched off.Type: GrantFiled: April 9, 2015Date of Patent: September 20, 2016Assignees: HONG FU JIN PRECISION INDUSTRY (WuHan) CO., LTD., HON HAI PRECISION INDUSTRY CO., LTD.Inventors: Jun-Yi Deng, Chun-Sheng Chen
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Patent number: 9438244Abstract: A circuit for controlling power within an integrated circuit comprises a plurality of circuit blocks; a global control signal routed within the integrated circuit; and a plurality of power control blocks. Each power control block is coupled to a corresponding circuit block of the plurality of circuit bocks and has a first input coupled to receive a reference voltage and a second input coupled to receive the global control signal. The global control signal enables, for each circuit block, the coupling of the reference voltage to the corresponding circuit block. A method of controlling power within an integrated circuit is also disclosed.Type: GrantFiled: October 28, 2014Date of Patent: September 6, 2016Assignee: XILINX, INC.Inventors: Santosh Kumar Sood, Brian C. Gaide, Steven P. Young
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Patent number: 9438241Abstract: An Integrated Circuit, a system, and a method are provided. The disclosed Integrated Circuit may include a plurality of pads exposing internal components of the Integrated Circuit to external circuits, a digital interface connectable to the plurality of pads, an analog interface connectable to the plurality of pads, and sensing circuitry configured to detect whether a digital circuit or an analog circuit is externally connected to the plurality of pads and based on such detection selectively connect at least one of the digital interface and analog interface to the plurality of pads.Type: GrantFiled: August 31, 2015Date of Patent: September 6, 2016Assignee: Avago Technologies General IP (Singapore) Pte. Ltd.Inventors: Milos Davidovic, Kurt Schweiger, Robert Swoboda
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Patent number: 9438196Abstract: An apparatus and method for a frequency based integrated circuit that selectively filters out unwanted bands or regions of interfering frequencies utilizing one or more tunable notch or bandpass filters or tunable low or high pass filters capable of operating across multiple frequencies and multiple bands in noisy RF environments. The tunable filters are fabricated within the same integrated circuit package as the associated frequency based circuitry, thus minimizing R, L, and C parasitic values, and also allowing residual and other parasitic impedance in the associated circuitry and IC package to be absorbed and compensated.Type: GrantFiled: August 18, 2014Date of Patent: September 6, 2016Assignee: Peregrine Semiconductor CorporationInventors: William R. Smith, Jaroslaw Adamski, Dan William Nobbe, Edward Nicholas Comfoltey, Jingbo Wang
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Patent number: 9438226Abstract: In some aspects of the invention, provided is a semiconductor device capable of compensating sufficiently instantaneous drop of power source voltage without enlarging device scale extremely. When digital circuit and power device driving circuit are formed on chip in the state connected to power source in common in parallel, for digital circuit of functional circuit remaining abnormal state after power source recovery and analog circuit and power device driving circuit of functional circuit retaining continuously normal state even before power source recovery, resistors are formed on chip in power source E side of the functional circuits, and in addition, capacitors are formed on chip 1 in parallel with the functional circuits, and consequently, it becomes possible to enlarge each resistance value of resistors as compared with a case of attaching externally resistors and capacitors in the entire chip.Type: GrantFiled: April 15, 2015Date of Patent: September 6, 2016Assignee: FUJI ELECTRIC CO., LTD.Inventor: Takanori Kohama
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Patent number: 9432019Abstract: A control chip for power saving is provided. The control chip is configured to operatively receive a first voltage and a first bias voltage. The control chip includes a microcontroller unit and a low power module. The low power module is coupled to the microcontroller unit. The microcontroller unit receives the first voltage to control the operation of at least one component under an operating mode and to stop receiving the first voltage under a power saving mode. The low power module operatively receives the first bias voltage. When the microcontroller unit switches from the operating mode to the power saving mode, the low power module operatively generates a first control signal to cause the microcontroller unit to stop receiving the first voltage. When the low power module detects a trigger signal, the power module operatively generates a second control signal to cause the microcontroller unit to continue receiving the first voltage.Type: GrantFiled: March 5, 2015Date of Patent: August 30, 2016Assignee: REALTEK SEMICONDUCTOR CORP.Inventors: Chih-Yuan Yang, Wen-Hsia Kung
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Patent number: 9431128Abstract: Disclosed herein is an apparatus that includes a fuse circuit including a fuse element, the fuse circuit configured to provide a first output signal having a first voltage or a second voltage responsive to a state of the fuse element, and a sense circuit configured to provide a second output signal having the first voltage or a third voltage responsive to the first output signal, the third voltage different from the second voltage.Type: GrantFiled: March 2, 2015Date of Patent: August 30, 2016Assignee: Micron Technology, Inc.Inventors: Yusuke Sakamoto, Kenji Yoshida
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Patent number: 9431322Abstract: According to one embodiment, a semiconductor device includes chips and a first selection circuit. Each of the chips has at least first and second vias for transmitting at least first and second address signals, these chips are stacked to be electrically connected via the first and second vias. The first selection circuit is provided in each chip, includes a logic circuit that selects a chip based on at least the first and second address signals, and supplies a result of operating the first and second address signals to the subsequent chip.Type: GrantFiled: November 24, 2014Date of Patent: August 30, 2016Assignee: KABUSHIKI KAISHA TOSHIBAInventor: Masaru Koyanagi