Abstract: Methods and apparatuses for measuring a phase noise level in an input signal are disclosed. An input signal can be delayed to generate a delayed version of the input signal. Next, a phase difference can be detected between the input signal and the delayed version of the input signal. A phase noise level in the input signal can then be determined based on the detected phase difference. The measured phase noise level can then be used to suppress phase noise in the input signal.

Abstract: A semiconductor apparatus includes a controller configured to generate a plurality of control signals for selecting an operation mode of the semiconductor apparatus in response to a number of input chip enable pulses, and an output driving unit configured to be operated according to the operation mode of the semiconductor apparatus based on the plurality of control signals.

Abstract: The present disclosure describes apparatuses and techniques of fast transient response for switching power regulators. In some aspects, a transconductance load is connected to a feedback amplifier of a switching power regulator that is operating in a discontinuous mode. This can be effective to dampen an indication, provided by the feedback amplifier, of voltage at an output of the switching power regulator while the regulator provides current to a load. Based on the dampened indication of the voltage, a current draw of the load is detected that exceeds the current provided to the load. Responsive to detecting the excessive current of the load, the switching regulator is transitioned to a continuous mode to provide an increased amount of the current to the load. Alternately or additionally, the increased amount of current can be allowed to exceed a nominal current limit protection threshold by a predefined amount of current, for a predefined number of switching cycles, or for a predefined amount of time.

Abstract: The present disclosure describes apparatuses and techniques of fast transient response for switching power regulators. In some aspects, a detection is made of a switching regulator's transition to a continuous mode of operation to provide current to a load. In response to the transition, a predefined current limit of the switching regulator's current-limit circuitry is increased effective to enable the switching regulator to draw an amount of input current that exceeds the predefined current limit. The switching regulator is then permitted to operate with the increased current limit for a predetermined number of cycles, which can be effective to enable the switching regulator to provide the current to the load more quickly.

Abstract: An inverting amplifier creates a voltage C using a reference voltage (voltage B) as a reference point. An adder composed of two input inverting amplifier circuits ultimately creates a voltage D by carrying out weighted addition of the voltage A and the voltage C. By using the voltage D created by an input front-end circuit, the internal functions of the control IC can prevent the operating points and control amounts for each function from being different relative to the input voltage and make it possible to distinguish voltage within the control IC from zero voltage when the lowest input voltage is received.

Abstract: A battery assembly includes a power module, a receptacle connector, a driving switch and a movable stop arm. The power module includes a battery control unit and a cell electrically connected to the battery control unit. The receptacle connector is disposed at the power module and electrically connected to the cell via the battery control unit. The receptacle connector includes an insertion opening. The driving switch is disposed corresponding to the receptacle connector and electrically connected to the battery control unit. A default setting of the driving switch is “switched off”. One end of the movable stop arm is outside of the insertion opening and blocks the same. The movable stop arm is movable toward the driving switch to touch and switch on the same.

Abstract: Techniques are disclosed relating to dual-edge triggered clock gater circuitry. In some embodiments, an apparatus includes dual-edge triggered clock gater circuitry configured to generate an output signal based on an input clock signal and a control signal that indicates whether to gate the input clock signal. In some embodiments, the clock gater circuitry includes first and second storage elements. In some embodiments, the clock gater circuitry includes multiplexer circuitry that selects between outputs of the first and second storage elements to generate the output signal. In some embodiments, the clock gater circuitry includes a third storage element configured to store an indication of which of the first and second storage elements stores a first digital value and which stores an inverse of the first digital value when not gating.

Abstract: Control circuits with energy recycling for envelope elimination and restoration and related methods are disclosed. A control circuit includes a filter module configured to condition an input power signal to provide an output power signal. An energy recapture module is electrically coupled to the filter module and is configured to capture a portion of residual energy from the filter module and return the portion of the residual energy to the input power signal. A control module is electrically coupled to the filter module and the energy recapture module and is configured to control the filter module to provide the output power signal and is further configured to control the energy recapture module to capture and return the portion of the residual energy to the input power signal.

Abstract: Disclosed is an op-amp circuit with current-controlled hysteresis that is insensitive to PVT variations. In the circuit, a digital output signal is output from an output buffer based on the output voltage at an output node of an op-amp. A current source is connected to the input side of the op-amp or one of multiple current sources is selectively connected to the input side and enabled when the digital output signal has a high value to provide falling edge hysteresis. Alternatively, a current source is connected to the reference side of the op-amp or one of multiple current sources is selectively connected to the reference side and enabled when the digital output signal is low to provide rising edge hysteresis. Alternatively, current sources are connected to both the input and reference sides and selectively controlled to provide either falling or rising edge hysteresis.

Abstract: A circuit for generating a negative voltage on the basis of a positive voltage, including: at least one first transistor between a first terminal for applying a potential greater than a reference potential and a first node; a first capacitive element between the first node and a second node, a control terminal of said first transistor being linked to the second node; a first switch between the first node and a second terminal for applying the reference potential; a second switch between the second node and a third terminal for providing said negative voltage; a third switch between the second node and the second terminal; and a second capacitive element between the third terminal and the second terminal.

Abstract: Disclosed examples include frequency divider circuits, comprising an even number 4 or more differential delay circuits coupled in a cascade ring configuration of a configurable length N, with N?K of the N delay circuits providing an inverted polarity output signal to a succeeding delay circuit in the cascade ring configuration to control an amount of overlap between phase shifted clock signals from the delay circuits.

Abstract: A MOS device includes first, second, third, and fourth interconnects. The first interconnect extends on a first track in a first direction. The first interconnect is configured in a metal layer. The second interconnect extends on the first track in the first direction. The second interconnect is configured in the metal layer. The third interconnect extends on a second track in the first direction. The third interconnect is configured in the metal layer. The second track is parallel to the first track. The third interconnect is coupled to the second interconnect. The second and third interconnects are configured to provide a first signal. The fourth interconnect extends on the second track in the first direction. The fourth interconnect is configured in the metal layer. The fourth interconnect is coupled to the first interconnect. The first and fourth interconnects are configured to provide a second signal different than the first signal.

Abstract: A charge pump circuit includes a plurality of stages. Each stage of the charge pump circuit includes: a first transistor, drain of the first transistor being output of the stage, source of the first transistor being input of the stage; a second transistor, gate of the second transistor being connected to source of the first transistor, drain of the second transistor being connected to drain of the first transistor, source of the second transistor being connected to gate of the first transistor, body of the second transistor being connected to body of the first transistor; and a third transistor, gate of the third transistor being connected to drain of the first transistor, drain of the third transistor being connected to source of the first transistor, source of the third transistor being connected to body of the first transistor and body of the third transistor.

Abstract: Various examples are directed to analog vacuum tube emulator circuits. In various examples, a vacuum tube emulator circuit may comprise a first circuit and a second circuit. The first circuit may be effective to receive, a first voltage, a second voltage, and a third voltage. The first circuit may be effective to develop, at an input of the first circuit, a first current based on the first voltage, the second voltage, and the third voltage. The first circuit may output the first current to an output node. The second circuit may be effective to receive the first voltage, the second voltage, and the third voltage. The second circuit may be effective to develop, at an input of the second circuit, a second current based on the first voltage, the second voltage, and the third voltage. The second circuit may output the second current to the output node.

Abstract: A nonvolatile three-terminal element is provided that operates by controlling a bandgap in an electron state of a graphene-based material. An ion conductor (5) having hydrogen ion or oxygen ion conductivity is provided between graphene oxide or graphene (hereinafter, referred to as GO) (6), and a gate electrode (1). In addition, a drain electrode (2) and a source electrode (3) are provided on a GO (6) side.

Abstract: A fast blocking switch includes, for example, an energy storage device, a first power switch and a second power switch. The energy storage device stores a charge for fast activation of the switches. The first switch is operable for coupling input current to an output terminal in response to the coupling of a potential supplied by the stored charge to a control terminal of the first switch. The second switch is operable for coupling a limited amount of the input current to the output terminal in response to the coupling of a potential supplied by the stored charge to a control terminal of the second switch.

Abstract: A semiconductor integrated circuit for a regulator, including: a control transistor; a control circuit; and a discharge circuit, wherein the discharge circuit includes: a constant current source circuit; a reference voltage generating circuit; a voltage comparator circuit; and a current amplification circuit, and wherein the control circuit is configured to control the control transistor in response to the control signal, and the discharge circuit is configured to operate the discharge transistor by the amplified current amplified by the current amplification circuit.

Abstract: A semiconductor device operates with electric power supplied from a direct-current power supply to an internal circuit in a state where a bypass capacitor is connected to a power supply terminal. The semiconductor device includes a load current control unit and a detection unit. The load current control unit changes an electric current supplied from the power supply terminal only in a predetermined operation period. The detection unit detects a voltage of the power supply terminal. The detection unit outputs a detection signal when the voltage is higher than a threshold upper limit in a case of being provided with the threshold upper limit. Alternatively, the detection unit outputs a detection signal when the voltage is lower than a threshold lower limit in a case of being provided with the threshold lower limit.

Abstract: A voltage regulator includes: a drive voltage generating part for generating a drive voltage and then apply the drive voltage to a drive line; an output transistor for outputting a voltage corresponding to a voltage value of the drive line as the internal source voltage; and a compulsory drive circuit including a capacitor element configured to receive the source voltage at one end, a first switching element for receiving a ground voltage and applying the ground voltage to the other end of the capacitor element by being set in an ON state over a period in which the selected operational mode is the standby mode, and a second switching element that connects the other end of the capacitor element to the drive line only for a predetermined period in an ON state when the operational mode transitions from the standby mode to the active mode.

Abstract: One embodiment relates to an apparatus for data communication between at least two in-package semiconductor dies. On the first semiconductor die in a package, a digital-to-analog converter (DAC) converts a plurality of binary signals to an analog signal. The analog signal is transmitted through a silicon bridge to a second semiconductor die. Another embodiment relates to a method of data communication between at least two in-package semiconductor dies. A plurality of binary signals is converted to an analog signal by a digital-to-analog converter on a first semiconductor die. The analog signal is transmitted through a silicon bridge to a second semiconductor die. Other embodiments, aspects and features are also disclosed.