Abstract: A method for testing a partially fabricated wafer is provided that comprises the following steps: providing a plurality of selectable devices under test (DUT) overlying a substrate of the wafer; biasing a second structure located in proximity to the DUT to have a first electrical state such that a first equivalent test structure is formed; determining a first parasitic parameter associated with the first equivalent test structure by applying a signal to the DUT while the second structure is in the first electrical state and measuring a response that is indicative of the first parameter; biasing the second structure to have a second electrical state such that a second equivalent test structure is formed; and determining a second parasitic parameter associated with the second equivalent test structure by applying a signal to the DUT while the second structure is in the second electrical state and measuring a response that is indicative of the second parameter.

Abstract: A device monitor for RF and DC measurement. The device monitor comprises a plurality of test cells arranged substantially in line. The test cell comprises a device under test, an input pad, an output pad and at least two reference pads. The input pad is electrically connected to an input of the DUT. The output pad is electrically connected to an output of the DUT. At least one of the reference pads is electrically connected to the DUT to provide a reference level. The input pad, the output pad and the reference pads are arranged substantially in line and at least one of the reference pads is located between the input pad and the output pad.

Abstract: In some embodiments, an apparatus includes an electronic device that has a ground to receive an electrostatic discharge. A radiation detector, mounted on the electronic device, generates a differential signal in response to the electrostatic discharge.

Abstract: An integrated circuit, in accordance with one embodiment of the present invention, includes a first device under test (DUT) module coupled to a first ring oscillator module and a second DUT module coupled to a second ring oscillator module. The first DUT module is biased such that interface traps are generated during a first mode. The generated interface traps result in a decrease in a first drive current of the first DUT module. The second device under test module is biased to maintain a reference drive current during the first mode. The operating frequency of the first ring oscillator module, during a second mode, is a function of the first drive current. The operating frequency of the second ring oscillator module, during the second mode, is a function of the reference drive current. The integrated circuit may also include a comparator module for generating an output signal as a function of a difference between the operating frequency of the first and second ring oscillator modules.

Abstract: Several embodiments of integrated circuit probe card assemblies are disclosed, which extend the mechanical compliance of both MEMS and thin-film fabricated probes, such that these types of spring probe structures can be used to test one or more integrated circuits on a semiconductor wafer. Several embodiments of probe card assemblies, which provide tight signal pad pitch compliance and/or enable high levels of parallel testing in commercial wafer probing equipment, are disclosed. In some preferred embodiments, the probe card assembly structures include separable standard components, which reduce assembly manufacturing cost and manufacturing time. These structures and assemblies enable high speed testing in wafer form. The probes also have built in mechanical protection for both the integrated circuits and the MEMS or thin film fabricated spring tips and probe layout structures on substrates.

Abstract: A conductive member has a first face adapted to be mounted on a board on which an inspection circuit is arranged and a second face adapted to be opposed to a device to be inspected. The conductive member being formed with a first through hole having a first diameter and communicating the first face with the second face. A contact probe is provided with a tubular body having a second diameter which is smaller than the first diameter, and a plunger retractably projected from one end of the tubular body. A first retainer is formed with a second through hole and opposing at least the second face of the conductive member so as to communicate the first through hole with the second through hole, so that the contact probe is retained in the conductive member while only the plunger is projected from one end of the second through hole. A second retainer is adapted to retain the one end of the tubular body concentrically with the first through hole.

Abstract: A testing system for check-in control in wafer testing. The testing system comprises a testing tool, an optical character recognition (OCR) device, and a controller. The testing tool performs a testing process of an article. The OCR device reads optical characters disposed on the article. The controller, connected to the testing tool and the OCR device, automatically initiates a check-in process for the article according to the read optical characters.

Abstract: A large-scale support carries semiconductor devices and at least one pair of common conductive regions in communication therewith. Each common conductive region is configured to be electrically connected with both a force contact and a sense contact of stress or test equipment. Such equipment includes at least one pair of force contacts for applying a force voltage across a pair of common conductive regions and, thus, across the support. A corresponding pair of sense contacts facilitates monitoring of a voltage applied across each of the semiconductor devices by the force contacts. Methods and systems for evaluating a voltage that has been applied to two or more semiconductor devices by way of a single pair of force contacts are also disclosed, as are methods and systems for, in response to a measured voltage, modifying the force voltage so that a desired voltage may be applied across each of the semiconductor devices.

Abstract: A landing system is provided for accurate placing of collection optics in a microscope. In one example, a solid immersion lens (SIL) is used for light collection, and the landing system is operated to place the SIL in contact with an IC. A proximity sensor is used for determining the SIL's position with respect to the IC. The arrangement is attached to a z-motion stage. During the placement procedure, the navigation is performed in steps and at each step the compression of the SIL is measured relative to its uncompressed state. When a measured compression exceeds a preset threshold, a SIL landing is recognized. In one example, after a landing is recognized, a further compression is imparted to the SIL in order to place the SIL in a focusing distance to the objective lens.

Abstract: A method for testing a semiconductor substrate forming a liquid crystal display device, which method enables a potential change corresponding to a defective condition of pixel cell driving circuits to be detected accurately even when a ratio of pixel capacitance to wiring capacitance is lowered with decrease in size or increase in definition of the liquid crystal display device. The method includes: a charge retaining step for making pixel capacitances connected to a plurality of pixel switches selected from all pixel switches connected to one data line retain charge; and a detecting step for simultaneously detecting the charge retained in a plurality of the pixel capacitances in the charge retaining step from the one data line.

Abstract: A flexible semiconductor test structure that may be incorporated into a semiconductor device is provided. The test structure may include a plurality of test pads designed to physically stress conductive lines to which they are attached during thermal cycling. By utilizing test pads with different dimensions (lengths and/or widths), the effects of thermal stress generated by a plurality of conductive lines having corresponding different dimensions may be simulated.

Abstract: A test circuit to test rise delay/fall delay performance on a semiconductor device may comprise a latch to latch data at its input responsive to a clock signal. The latch may source an output signal related to the data latched. A buffer chain may be configured to serially propagate the signal sourced by the latch from the latch output back to the clock input, as the clock signal. A reset/set input of the latch may be configured to receive a reset/set signal from an intermediate node of the buffer chain.

Abstract: A method of engaging electrically conductive test pads on a semiconductor substrate having integrated circuitry for operability testing thereof includes: a) providing an engagement probe having an outer surface comprising a grouping of a plurality of electrically conductive projecting apexes positioned in proximity to one another to engage a single test pad on a semiconductor substrate; b) engaging the grouping of apexes with the single test pad on the semiconductor substrate; and c) sending an electric signal between the grouping of apexes and test pad to evaluate operability of integrated circuitry on the semiconductor substrate. Constructions and methods are disclosed for forming testing apparatus comprising an engagement probe having an outer surface comprising a grouping of a plurality of electrically conductive projecting apexes positioned in proximity to one another to engage a single test pad on a semiconductor substrate.

Abstract: A probe card assembly includes a printed circuit board with tester contacts for making electrical connections to a semiconductor tester. The probe card assembly also includes a probe head assembly with probes for contacting a semiconductor device under test. One or more daughter cards is mounted to the printed circuit board such that they are substantially coplanar with the printed circuit board. The daughter cards may contain a circuit for processing test data, including test signals to be input into the semiconductor and/or response signals generated by the semiconductor device in response to the test signals.

Abstract: A stackable ball grid array (BGA) or fine ball grid array (FBGA) semiconductor package particularly suitable for board-on-chip or chip-on-board applications in which a low profile BGA or FBGA semiconductor package is needed. The stackable ball grid array (BGA) or fine ball grid array (FBGA) provides a semiconductor package that is capable of being burned in and tested in a more efficient and cost effective manner than prior known BGA or FBGA semiconductor packages. A high density, low profile memory module incorporating a plurality of the disclosed BGA or FBGA semiconductor packages in a stacked arrangement is further disclosed.

Abstract: In a method of testing a 3D packaged IC, the dies are tested under power by mounting on a specifically designed printed circuit board with a window in it for testing the die sequentially from below using a laser beam tester. The die found not to be defective is partially removed in sequential manner to allow the next higher die to be tested. The partial removal of dies is achieved by grinding a window in them using “ChipUnzip” techniques.

Abstract: In one embodiment, an anti-wafer structure includes a silicon on insulator (SOI) layer and a plurality of probe dice formed on the SOI layer. Each of the probe die may have a pad layout corresponding to a pad layout of a die on a wafer under test. A plurality of holes may extend through the SOI layer and the plurality of probe dice, with each hole corresponding to a pad on a probe die. The anti-wafer structure may be advantageously used in an advanced probe card. Techniques for fabricating an anti-wafer and an advanced probe card are also disclosed.

Abstract: An arrangement for obtaining measurable voltage signals in a utility meter includes a first connection to a phase of a power line, a second connection to a reference of a power line, a voltage divider circuit, and a series inductor. The voltage divider circuit is disposed on a circuit board and is coupled between a first node and the second connection. The voltage divider circuit has an output configured to provide measurable voltage signals to a circuit operable to generate voltage measurement information. The series inductor is disposed apart from the circuit board and is configured for current limiting. The series impedance element is coupled between the first connection and the first node.

Abstract: Systems and methods for frequency specific closed loop feedback control of integrated circuits. In one embodiment, a plurality of controllable inputs to an integrated circuit is adjusted to achieve a frequency specific predetermined value of a dynamic operating indicator of the integrated circuit at the desired specific operating frequency. The predetermined value is stored in a data structure within a computer usable media. The data structure comprises a plurality of frequency specific predetermined values for a variety of operating frequencies. An operating condition of an integrated circuit is controlled via closed loop feedback based on dynamic operating indicators of the measured behavior of the integrated circuit.

Abstract: In one embodiment, a probe for testing integrated circuits includes a body having a tip and a hardening material on the tip. The hardening material helps improve the hardness of the tip. The hardening material thus allows the probe to reliably penetrate a layer to make a good electrical connection with a contact point under the layer, for example. In one embodiment, an electrically conductive coating is deposited over the hardening material.