Abstract: A packaged semiconductor device uses built-in self test to characterize voltage between points within the semiconductor die during a current discontinuity generated in the semiconductor die. The semiconductor die is operated to generate a current discontinuity, or several sequential current discontinuities, and the voltage is measured with an on-chip ADC. Measuring the voltage within the semiconductor die, rather than measuring at external test points, provides a more accurate prediction of device operation. Multiple test points are measured using a multiplexer, multiple ADCs, or by reconfiguring an FPGA. Impedance versus frequency information of the greater power distribution system connected to the semiconductor die is obtained by transforming the voltage and current through the semiconductor die measured during a current discontinuity.

Abstract: An embodiment of the present invention is a technique to monitor on-die device power grid. A sensor circuit generates a ground reference (GR) signal and N power reference (PR) signals forming a ladder according to a programmable configuration. The GR signal tracks a device ground signal of a device and the PR signals track a device power signal of the device. A comparator circuit compares the GR signal with the N PR signals to provide N comparison output signals, the N comparison output signals indicating position and time that the GR reference signal moves across the ladder.

Abstract: An inspection method including measuring a height of a load cell of a load detecting mechanism using a laser length measuring mechanism, obtaining a first rise amount of the load detecting mechanism from a measuring position of the load detecting mechanism up to a contact starting position, measuring a height of an electrode of a wafer using the laser length measuring mechanism, and obtaining a second rise amount of a main chuck up to the contact starting point of the electrode with the probe based on a difference between a measuring height of the electrode of the wafer and the measuring height of the load detecting mechanism.

Abstract: A process condition measuring device and a handling system may be highly integrated with a production environment where the dimensions of the process condition measuring device are close to those of a production substrate and the handling system is similar to a substrate carrier used for production substrates. Process conditions may be measured with little disturbance to the production environment. Data may be transferred from a process condition-measuring device to a user with little or no human intervention.

Abstract: A method for failure analysis of small contacts in integrated circuits is provided. A number of opposing electrical contacts is configured to contact a sample in an offset pattern such that any one electrical contact may contact more than one conductor in the sample and any opposing electrical contact is offset-positioned to contact no more than one of the conductors contacted by the one electrical contact.

Abstract: A method of electrical testing devices such as integrated circuits that include conductive pads formed on the surface. A material having a desired bulk resistivity and viscosity is applied to either the device or the electrical probe prior to testing. The application of the material has been found to substantially reduce the need for cleaning of the probe.

Abstract: A supervisory system and method including a voltage detection circuit, a status signal interface, a memory, and a supervisory processor configured to predict a pending low power condition, to save status parameters, and to take actions to manage a plurality of processors receiving power from a power source susceptible to low voltage conditions, to stabilize the processors prior to and during a low voltage condition, and to restart the processors based on the status parameters.

Abstract: Detecting a connection between two circuits utilizing a high-speed interface. Interface circuitry internal to a computing device performs an initialization process between two processors automatically to determine the state of the interface connection. Test circuitry retrieves the interface state from the interface circuitry. Neither the configuration process, the interface circuitry or the test circuitry require full functionality of an IC on which they reside in order to operate.

Abstract: A testing device that tests an electronic device includes a detection-voltage outputting unit operable to output a current detection voltage based on a power source current that the electronic device receives from a power source, a transmission line operable to transmit the current detection voltage, a detection amplifier operable to output an amplifier output voltage based on the current detection voltage received through the transmission line, a switching unit operable to select whether the current detection voltage is supplied to the detection amplifier, an integrator operable to output an integral value that is obtained by integrating values based on the amplifier output voltage, and a decision unit operable to decide whether the electronic device is good or bad based on the integral value.

Abstract: A plurality of semiconductor devices are provided on a carrier for testing or burning-in. The carrier is then cut up to provide single chip-on-carrier components or multi-chip-on-carrier components. The carrier is used as a first level package for each chip. Thus, the carrier serves a dual purpose for test and burn-in and for packaging. A lead reduction mechanism, such as a built-in self-test engine, can be provided on each chip or on the carrier and is connected to contacts of the carrier for the testing and burn-in steps. The final package after cutting includes at least one known good die and may include an array of chips on the carrier, such as a SIMM or a DIMM. The final package can also be a stack of chips each mounted on a separate carrier. The carriers of the stack are connected to each other through a substrate mounted along a side face of the stack that is electrically connected to a line of pads along an edge of each carrier. The carrier is formed of a flex material.

Abstract: The quality and reliability of electro-optical modules can be improved, for instance, through improved testing and burn-in of an electro-optical sub-assembly. Reliability can also be enhanced through better methods of constructing an electro-optical module. By arranging both an electrical interface and an optical interface on a sub-assembly, for instance, testing can be performed on both interfaces in a single testing process. Burning-in an electro-optical sub-assembly can also improve the reliability of the module by identifying defects. A method of forming an electro-optical module can provide improved reliability by testing and/or burning-in an electro-optical sub-assembly before assembling the module.

Abstract: The invention(s) relates to a wafer test system including a circuit to communicate an overdrive to a chuck, the chuck moving a wafer towards a probe head responsive to the overdrive, a circuit to measure a contact resistance of at least one channel in each of a plurality of dies associated with the wafer using the probe head, a circuit to compute a per channel standard deviation responsive to measuring the contact resistance, a circuit to compare the standard deviation on the at least one channel to a threshold, and a circuit to increase the overdrive responsive to the comparison.

Abstract: A method for testing a circuit includes determining at least one performance characteristic of the circuit based on a functional relationship between excitation signals or on a functional relationship between measurement devices. The method is implemented either as a part of a built-in self test circuit of an integrated circuit or for production testing.

Abstract: An interconnect for testing semiconductor components includes a substrate, and interconnect contacts on the substrate for electrically engaging terminal contacts on the components. The interconnect also includes one or more cavities in the substrate which form flexible segments proximate to the interconnect contacts. The flexible segments permit the interconnect contacts to move independently in the z-direction to accommodate variations in the height and planarity of the terminal contacts. In addition, the cavities can be pressurized, or alternately filled with a polymer material, to adjust a compliancy of the flexible segments. Different embodiments of the interconnect contacts include: metallized recesses for retaining the terminal contacts, metallized projections for penetrating the terminal contacts, metallized recesses with penetrating projections, and leads contained on a polymer tape and cantilevered over metallized recesses.

Abstract: Improved methods and apparatus are provided for the handling and testing of semiconductor devices. One embodiment comprises a die carrier for one or more semiconductor dice having very fine pitch electrical I/O (input/output) elements. The semiconductor dice are temporarily attached to the die carrier in singulated form to enable testing the dice with conventional contact technology. The die carrier may include a flex circuit base substrate and a rigid support frame. Further embodiments comprise materials and methods for attaching the semiconductor dice to the die carrier and for providing a temporary electrical connection with the semiconductor dice during testing. Exemplary materials for providing the temporary electrical connection may comprise a conductive film or tape, a conductive or conductor-filled epoxy, resin or RTV adhesive-based materials, a water-soluble material impregnated with a conductive filler or non-reflowed solder paste.

Abstract: A system and method for testing substrates is generally provided. In one embodiment, a test system for testing a substrate includes a load lock chamber, a transfer chamber and a test station. The load lock chamber and the test station are disposed on top of one another and coupled to the transfer chamber. The transfer chamber includes a robot adapted to transfer a substrate between the load lock chamber, which is at a first elevation, and the test station, which is at a second elevation. In another embodiment, a test station is provided having a turntable adapted to rotate the substrate. The turntable enables the range of motion required to test the substrate to be substantially reduced while facilitating full test and/or inspection of the substrate.

Abstract: Test modules, systems, and methods employing capacitors for the testing of the solder joint connections between a printed circuit board (PCB) and a socket of a device are presented in embodiments of the current invention. A test module having capacitors in parallel, and in particular embedded capacitors, can be used to test tied traces and their solder joint connections by measuring the total capacitance of the capacitors. Embodiments of the current invention present no-power tests that can be used with a variety of testing platforms and test fixtures, such as in-circuit testing (ICT) and manufacturing defect analysis (MDA.) Additionally, the test module can be used with a variety of sockets, such as a ball grid array, a pinned grid array, and a land grid array.

Abstract: A process for testing circuit boards for serviceability is designed such that a flexible layer (2) that is initially impermeable to current is placed directly on at least one side of the circuit board (1), making contact, and it is dynamically connected to a current conductor (3), the layer (2) is then energized and then a current passage is partially created at the contact points that delimit the respective conductor path (5) that is to be tested, and then the flow of current in the conductor path (5) is measured using the current conductor (3).

Abstract: A method for calibrating voltage sensors in a switchboard, using a communication bus which comprises the following steps: i. performing a measurement using a first voltage sensor; ii. transmitting an information derived from said measurement to an electronic device, through the communication bus; iii. using said information to calibrate a second voltage sensor.

Abstract: A defect inspecting apparatus in which a plurality of probes to measure electric characteristics of a sample including a fine wiring pattern are combined with a charged-particle beam unit includes graphic user interfaces (GUI) to simply control the plural probes. The apparatus includes a probe image processing unit to display the plural probes on a display; a selecting unit to select, from the probes displayed on the display, a probe to be operated; and a display unit to simultaneously display the probe selecting unit and information indicating that the selected probe is an operable probe, or the probe is in a non-selected state.