Abstract: A hermetic multilayered ceramic semiconductor package for micromachined semiconductor devices. A low temperature co-fired ceramic assembly has a cavity and a top and bottom surface. Several vias extend between the top and bottom surfaces and several solder spheres are located on the top surface and are electrically connected to the vias. A micromachined semiconductor device abuts the bottom surface and covers the cavity such that a movable portion of the micromachined semiconductor device is unconstrained to move within the cavity. Solder is used to connect the vias to solder bumps on the semiconductor device. A seal ring is located between the micromachined semiconductor device and the ceramic assembly for hermetically sealing the micromachined semiconductor device.

Abstract: A “paddle-under-lead” (PUL) leadframe has the inner portions of an I.C. package's leads extend along the top of a paddle, to which they are affixed. An I.C. die is affixed to the top of the inner leads to form an I.C. package. Because the die is affixed directly to the leads, heat generated by the die is conducted out of the package via the package's leads, with the paddle serving as a heat spreader and heat sink. The leadframe's inner leads are affixed to the paddle, rather than separated from it as is done conventionally; this enables a larger die size to be accommodated within the same standard package size. A bifurcated inner lead design, usable with the PUL leadframe and others, divides the inner portions of an I.C. package's leads into laterally offset upper and lower sections, with the upper section serving as a wedge bond shelf and the lower section downset from the upper section.

Abstract: A semiconductor device according to the invention of the present application comprises a substrate having a surface on which interconnections are formed, a semiconductor element connected to the interconnections and mounted on the substrate, and a conductive map for covering the semiconductor element electrically connected to a ground potential. Owing to the provision of the conductive cap for covering the semiconductor element in this way, the semiconductor device can prevent the emission of an electromagnetic wave to the outside and can be prevented from malfunctioning due to an external electromagnetic wave.

Abstract: An integrated circuit utilizing copper wiring has copper bond pads which are covered with a passivation layer to prevent unwanted reactions of the copper with metals which are bonded to it. The passivation layer can be an intermetallic of copper and titanium or a stacked layer of CuTix/TiN. Various nitrides can also be used, such as tungsten nitride, tantalum nitride, titanium silicon nitride, tungsten silicon nitride, and tantalum silicon nitride.

Abstract: A wafer frame for fixing and handling 200 mm wafers is produced with a significantly reduced weight as compared to a metal wafer frame, while maintaining mechanical and thermal material properties. This is accomplished by producing the wafer frame from a plastic with a glass fiber content of from 1 to 40% by weight.

Abstract: A circuit board with protrusions at desired locations on a wiring pattern that on the surface of the board. The protrusions are made of the same conductive material used in the wiring pattern, and formed unitarily and simultaneously with the wiring pattern. Conductive material is filled into grooves having different depths and formed on a film. The filled conductive material is transferred onto the board, and then fired. Thus the circuit board is manufactured. Semiconductor devices and general-purpose components are mounted on the circuit board, whereby a semiconductor device can be manufactured with high reliability and at an inexpensive cost.

Abstract: A highly reliable semiconductor device having a contact hole with a sufficient area can be obtained. An interlevel insulating film is formed on a conductive region having a first width. A through hole which exposes the conductive region is formed at the interlevel insulating film. A coating film is formed on the interlevel insulating film. In the coating film, an opening having a second width larger than the first width is formed in a region located on the through hole. An interconnect line is formed in a region located on the opening. A conductor film for electrically connecting the conductive region and the interconnect line is generated within the through hole.

Abstract: A method of laying out traces for connection of bond pads of a semiconductor chip to a printed wiring board or the like and the layout. There is provided a substrate having top and bottom surfaces with a plurality of rows and columns of vias extending therethrough from the top surface to the bottom surface and having a solder ball secured at the bottom surface to each via. A plurality of pairs of traces is provided on the top surface, each trace of each pair of traces extending to a different one of the vias and extending to vias on a plurality of the rows and columns, each of the traces of each pair being spaced from the other trace by a ball pitch, being maximized for identity in length and being maximized for parallelism and spacing. Each of the traces of a pair is preferably be further maximized for identity in cross-sectional geometry. A differential signal pair is preferably applied to at least one of a pair of traces.

Abstract: A dual leadframe package. A chip including a first surface and a second surface is provided. A gate and a first source/drain region are located on the first surface, and a second source/drain region is located on the second surface. A first lead including a first innerlead and a first outerlead and a second lead including a second innerlead and a second outerlead are provided. The first innerlead is coupled to the first source/drain region, and the second innerlead is coupled to the gate. A conductive plate including a top surface and a bottom surface is provided, and the top surface is coupled to the second source/drain region. A packaging material seals the chip, the first innerlead, the outerlead and a portion of the conductive plate. The bottom surface, the first outerlead and the second outerlead are exposed.

Abstract: A semiconductor package, and a method for fabricating the package are provided. The package includes a semiconductor die, a lead frame, and a metal foil die mounting plate adapted to mount the die to the lead frame. In addition, the die mounting plate provides a thermally conductive path from the die to terminal leads of the package. Further, the die mounting plate can be configured to perform electrical functions, such as providing ground/power planes for the package, and adjusting an impedance of signal paths through the package. In a first embodiment the package can be fabricated using a tape under frame lead frame. In a second embodiment the package can be fabricated using a lead under chip lead frame.

Abstract: A semiconductor package includes a semiconductor die mounted on an upper surface of a substrate. A number of wire bonds electrically connect between a number of bonding pads on the upper surface of the substrate and a number of bonding pads on an upper surface of the semiconductor die. A fixing portion surrounds the semiconductor die and covers a mediate portion of each wire bond. Encapsulating material is molded over the semiconductor die and the wire bonds to form an encapsulant. In an alternative embodiment, the fixing portion is provided on the upper surface of the substrate adjacent to a mold gate of the substrate where the wire sweeping is most likely to occur while molding. The fixing portion does not cover the semiconductor die to avoid thermal strain acting on the semiconductor die due to the different coefficients of thermal expansion between the fixing portion and the encapsulant.

Abstract: A semiconductor device is provided which is highly reliable and operable at fast speed and low noises. In this semiconductor device, there are provided a power wiring section 1003a, a ground wiring section 1003b and a signal wiring section 1003c are formed on one level. The power wiring section or the ground wiring section is formed adjacently on both sides of at least one part of the signal wiring section.

Abstract: A semiconductor device includes a F-doped interlayer insulation film and a high-refractive index insulation film having a refractive index higher than a refractive index of the F-doped interlayer insulation film, such that the high-refractive index insulation film is disposed at least one of a top side and a bottom side of the F-doped interlayer insulation film.

Abstract: The present invention discloses a bump nest which allows a semiconductor device to be temporarily connected with a package without having to be fused to the package. The disclosed temporary interconnect includes a contact group comprising at least three projecting contact elements. Each of the respective contact elements includes a projecting contact guide, which is concentrically located on an encircling contact. The projecting contact guides and the encircling contact are spaced in a manner so as to surround a ball or a bump of the semiconductor device. In the preferred embodiment, the temporary interconnect may also include a base pad on which each of the encircling contacts is accurately positioned to surround the ball or bump.

Abstract: A microelectronic component for mounting a rigid substrate, such as a hybrid circuit to a rigid support substrate, such as a printed circuit board. The microelectronic component includes a rigid interposer which may have a chip mounted on its first surface; a pattern of contacts on the rigid interposer; a flexible interposer overlying the second surface of the rigid interposer; a pattern of terminals on the flexible interposer; flexible leads; and solder coated copper balls mounted on the flexible interposer. The microelectronic component may have a socket assembly mounted on the first surface of the rigid interposer. The microelectronic component may be mounted on a rigid support substrate.

Abstract: A wafer-level chip scale package. The structure is applicable in packing at least two dies into a same package. The volume of the package is approximately equal to the total volume of the packed dies. A first die is provided. A pad redistribution step is performed on the first chip. Using flip chip technique, a second die is connected onto the first die. The first die has a surface area larger than that of the second die. Using a molding process, a molding material is infilled into spaces between the first and the second die. In addition, bumps are formed on the first chip with one ends thereof exposed and the other part covered by the molding material. Solder balls are formed on the exposed end of the bumps as terminals to electrically connect an external circuit or device.

Abstract: A connection component for a semiconductor chip includes a support structure having a top surface including a dielectric material and a bottom surface. The support structure includes a central portion, a peripheral portion and one or more gaps extending substantially between the central portion and the peripheral portion. A bus overlies the top surface of the support structure. The each bus has an outer edge which overlies the peripheral portion of the support structure and an inner edge which overlies the one or more gaps. The support structure also includes one or more electrically conductive leads having first ends secured to the central portion and second ends overlying the gaps and being secured to the inner edge of the bus. The second ends of the leads are displaceable relative to the bus in response to bonding forces being applied to the leads for engaging contacts on a semiconductor chip.

Abstract: An ohmic electrode structure includes an n-InxGa1−xAs layer where 0<x≦1; a Pt or Pd layer provided on the n-InxGa1−xAs layer; and at least one metal layer provided on the Pt or Pd layer. A semiconductor device includes a substrate; a first semiconductor layer having a p-type conductivity provided on the substrate; a second semiconductor layer having an n-type conductivity provided on the substrate; an ohmic contact layer provided on the first semiconductor layer; a barrier layer provided on the second semiconductor layer; a first electrode provided on the ohmic contact layer; and a second electrode provided on the barrier layer. The ohmic contact layer and the barrier layer are each formed of a material selected from the group consisting of Pt and Pd.

Abstract: A structure and method for making copper interconnections in an integrated circuit are described. The structure is a damascene copper connector whose upper surface is coplanar with the upper surface of the insulating layer in which it is embedded. Out-diffusion of copper from the connector is prevented by two barrier layers. One is located at the interface between the connector and the insulating layer while the second barrier is an insulating layer which covers the upper surface of the connector. The damascene process involves filling a trench in the surface of the insulator with copper and then removing the excess by chem.-mech. polishing. Since photoresist is never in direct contact with the copper the problem of copper oxidation during resist ashing has been effectively eliminated.

Abstract: Chip stack type semiconductor package and method for fabricating the same, the package including a lower chip having a center pad formation surface defined at a bottom thereof, an upper chip stacked on the lower chip by being adhered to a top surface of the lower chip having no center pad formed thereon and having a center pad formation surface defined at a top surface thereof, both surface adhesive insulating tapes attached on regions spaced from, and positioned left and right sides of respective center pads formed in the center pad formation surfaces of the lower chip and the upper chip, leads having inner lead portions inside of a molded body of an encapsulation resin and outer lead portions exposed outside of the molded body and both end portions of the leads attached to the both surface adhesive insulating tapes attached on left and right sides of the center pads of the upper chip and to the both surface adhesive insulating tapes attached on left and right sides of the center pads of the lower chip oppos