Abstract: 052450152 A power noise preventing circuit for a microcontroller unit (MCU) is provided that prevents an erroneous operation of the MCU caused by power supply noise. The power noise preventing circuit for the MCU can include a power fail detecting circuit that controls a power fail signal by comparing supplied power to a preset fail voltage of a MCU and a system clock generating circuit that receives a clock signal and generates a first system clock signal that determines a state of a system. A clock freezing and synchronizing circuit fixedly outputs a second system clock signal at a state of the first system clock signal when the power falls below the preset fail voltage and the power fail signal is enabled. The clock freezing and synchronizing circuit further outputs the second system clock signal synchronized with the first system clock signal when the power fail signal is disabled.

Abstract: A logic analyzer uses a single tapped delay line and a single array of sampling cells for high speed digital signal acquisition, by controlling both edges of a substantially 50% duty cycle clock signal to drive a delay line buffer chain. The chain operates continuously; there being no need for interruptions for precharge intervals. Thus, the need for a second delay line buffer chain is eliminated.

Abstract: A low voltage cascode frequency conversion mixer circuit is provided. In place of a conventional current source, an LC tank circuit is used. This makes the circuit function as a mixer only over a narrow band of frequencies centred at the resonance frequency of the LC tank circuit. The circuit mixes an input signal with a local oscillator signal. Advantageously, a lower supply voltage may be used because a smaller DC drop exists across the tank circuit than does across conventional current sources. The circuit may also be used as an amplifier by connecting a DC bias voltage in place of the local oscillator.

Abstract: A method and apparatus comprising a first circuit configured to generate a first output in response to a first input, a second circuit configured to present a second output in response to a second input, and a third circuit configured to generate a first voltage signal and a second voltage signal in response to the first output and said second output. The first voltage signal may be above the positive supply and the second voltage signal may be below the negative supply.

Abstract: An output buffer is provided which receives an input signal and drives an output terminal. The output buffer has a first driver and a second driver for driving the output terminal to a voltage level corresponding to a logic value of the input signal. The second driver has a greater (current) driving capacity than the first driver. The output buffer also has control circuitry which detects a transition in the logic value of the input signal. In response, the control circuitry generates a particular pulse aligned with the input signal logic value transition having a particular constant voltage level for a predetermined time period. Furthermore, the control circuitry delays the second circuit from driving the output terminal to a complementary voltage level corresponding to the logic value to which the input signal transitions during the predetermined time period.

Abstract: Temperature compensation of LDMOS devices as are employed in high power amplifiers follows from replacing the voltage source and resistive divider that feed the sensing diode of prior art temperature compensators for transistor amplifiers, with a current source feeding the sensing diode in a manner that is substantially independent of voltage variations which follow from temperature change. Such current variations as result from temperature change, in the circuit of the invention, produce variations in the bias voltage at the gate of the LDMOS power transistor which are many times less than the temperature coefficient of the LDMOS device, in producing virtually error-free temperature compensation.

Abstract: A reference voltage generator includes a voltage controlled oscillator which has fixed and accurate relationship between a frequency of an oscillation signal and a voltage supplied thereto, a reference frequency oscillator for generating a reference frequency signal of high accuracy and stability, a phase comparator for detecting a phase difference between the oscillation signal of the voltage controlled oscillator and the reference frequency signal, a low pass filter for smoothing a detection signal from the phase comparator, a gain adjust circuit for amplifying a signal from the low pass filter, a voltage adder for providing a sum of voltages from the gain adjust circuit and an offset voltage to the voltage controlled oscillator, and a phase clock loop formed by the phase comparator, low pass filter, gain adjust circuit and voltage adder to null the phase difference by regulating a control voltage applied to the voltage controlled oscillator.

Abstract: A high voltage generating circuit is disclosed, which reduces power consumption due to unnecessary operations. The high voltage generating circuit includes a charge pump for pumping an output voltage in response to a first pump control signal and a second pump control signal which are synchronizing signals, a first level detector operated by an externally applied enable signal and for detecting a first level from the output voltage and outputting a first level signal, a first pump controller for generating a control signal using the first level signal and a reference signal, and outputting the first pump control signal using the control signal and an externally applied inverted clock signal, a second level detector operated by the control signal and for detecting a second level from the output voltage and outputting a second level signal, and a second pump controller for outputting the second pump control signal using the second level signal, the reference signal and an externally applied clock signal.

Abstract: A current control circuit is provided which is capable of maintaining a constant DC current flowing in a load resistor irrespective of the resistance value of a load resistor connected to a connection terminal. To this end, a constant current circuit (21) is connected to a RING terminal (2), which acts as the connection terminal. The constant current circuit (21) controls a current drive circuit (6) in response to a voltage at the RING terminal (2) to ensure that a DC current flowing in a power feed resistor (4) is kept constant. Due to the fact that DC current flowing in the load resistor irrespective of the resistance value of the load resistor is kept constant, the burden placed on a power supply of a subscriber line interface in a telecommunications network is no longer increased. Also, there no longer arises a need for increasing a power feed resistance and the rating of a power feed transistor, which, in turn, leads to a reduction in manufacturing cost.

Abstract: The frequency doubling circuit according to the present invention includes first and second pulse generating circuits generating first and second pulse trains based on a periodic input signal. The second pulse train is out of phase with the first pulse train, and a combining circuit combines the first and second pulse trains to generate a periodic output signal having twice the frequency of the periodic input signal. Both the first and second pulse generating circuits include first and second charge storage devices, with the second charge storage device having half the storage capacity of the first charge storage device.

Abstract: A device for generating a voltage pulse in a low-voltage integrated circuit includes a capacitor and a control circuit. An input signal having negative pulses is received by the device. The input signal has a high level corresponding to a level of a logic supply voltage for the device, and a low level corresponding to zero volts. The control circuit includes a first and a second circuit element. The first circuit element transmits the low level of the input signal to a second terminal of the capacitor and also provides the capacitor a charging path. The second circuit element transmits the low level of the input signal to a first terminal of the capacitor with a predetermined delay so that a negative pulse between the high level and a negative level is provided at the second terminal of the capacitor in response to the input signal.

Abstract: A digital PLL circuit recovers a clock signal from an analog baseband signal. The PLL circuit has a phase comparator. The phase comparator provides a loop filter with a control value for a period of the recovered clock signal after a determination is made. If the determination is that the baseband signal has crossed a transition level, the control value corresponds to a time difference between a sampling point and a transition-level crossing point of the baseband signal. If the determination is that the baseband signal has not crossed the transition level, the control value is 0. The PLL circuit shortens a lockup time and provides stable operation even if the baseband signal involves an offset.

Abstract: To compensate for process, activity and environmental variations in a semiconductor device, a ratio of a transistor on-current to a transistor off-current within the semiconductor device is detected. The detected ratio is compared with a target ratio to adjust a bias potential of the semiconductor device to bring the detected ratio of the transistor on-current to the transistor off-current to the target ratio.

Abstract: A first complementary metal oxide semiconductor (CMOS) current reference circuit (100, 500) has a first and a second current mirror (110, 150) and is implemented using one of bulk wafer technology and silicon on insulator (SOI) technology. The first current mirror (110) has an output stage (130) that includes at least one cascode coupled field effect transistor (FET) (125) having one of a source tied well (when implemented using bulk wafer technology) or a source tied body (when implemented using SOI technology). A second CMOS current reference circuit (600, 800) has a first and a second current mirror (650, 610) and is implemented using SOI technology. The first current mirror (650) has a first bias FET (161) having a gate tied body.

Abstract: A temperature sensing circuit suitable for integration with a power semiconductor device (MOSFET/IGBT) includes temperature-sensing p-n diode means (D1, D2, etc . . . ) integrated together with first and second IGFETs (M1 and M2). A current path through the temperature-sensing p-n diode means (D1, D2, etc . . . ) provides a voltage drop (Vf) having a negative temperature coefficient. The IGFETs (M1 and M2) are coupled in separate current paths from each other so as to have separate gate-to-source voltage signals (Vgs1 and Vgs2) between their source and gate electrodes (s and g). The gate-to-source voltage (Vgs1) of the first IGFET (M1) has a negative temperature coefficient of greater magnitude than the temperature coefficient (if any) of the gate-to-source voltage (Vgs2) of the second IGFET (M2). One of the source and gate electrodes (s or g) of the first IGFET (M1) is coupled to the p-n diode means (D1, D2, etc . . .

Abstract: In a control voltage producing apparatus, either a pulse-duration modulation signal or a pulse-width modulation signal, which are generated in response to a digital control signal, is from a first buffer circuit to an averaging circuit so as to be averaged. A power supply voltage is supplied from a first voltage source to this first buffer circuit. Then, the averaged signal is supplied to a control voltage producing circuit for producing a target control voltage. When a control voltage is produced, the same output voltage as that of the first buffer circuit is generated by a second buffer circuit, and then is supplied to the control voltage generating circuit and an operation control circuit. In response to the output voltage derived from the second buffer circuit, the operation control circuit applies the power supply voltage to the control voltage producing circuit so as to cause this control voltage producing circuit to be operable.

Abstract: A voltage regulator of the type comprising a linear filter, a comparator, and a stretcher filter which are connected in cascade with one another between an input terminal and an output terminal of the regulator. The input terminal receives an error signal as converted by the comparator into a square-wave error signal, and the output terminal deliveres a square-wave output control signal which has a stretched duty cycle over the square-wave error signal by a time delay introduced from the stretcher filter. The regulator further comprises a non-linear filtering section for the error signal which is connected between the input terminal of the regulator and the linear filter and has linear gain with the error signal below a first value, gain approximately of unity with the error signal between the first value and a second value, and zero gain with the error signal above the second value.

Abstract: A circuit for the glitch-free changeover between digital signals includes a multiplexer having a multiplicity of signal input terminals, signal select terminals and a signal output terminal. Furthermore, the circuit includes a counter logic unit for counting pulses in the output signal of the multiplexer and for outputting a count signal when a specific count value is reached. A delay logic unit delays a multiplexer select signal and outputs a switching signal and a delayed multiplexer select signal. During a set switching signal the counter logic unit is activated and the circuit output is deactivated.

Abstract: A charge pump circuit comprises a plurality of capacitors arranged to charge and discharge for generating a charged-up voltage. An oscillation circuit generates a clock signal to be applied to the plurality of capacitors to alternately charge and discharge these charge-up capacitors. A monitoring circuit detects electrical potentials on at least two of the charge-up capacitors and controls the clock signal. An oscillating condition of the oscillation circuit based on the electrical potentials on the at least two of the charge-up capacitors.

Abstract: A substrate biasing circuit includes a logical threshold potential output circuit including transistors formed on a semiconductor substrate and generating a logical threshold potential. A potential compare control circuit compares the logical threshold potential with a reference potential and generating a control potential based on a comparison result. A substrate bias generating circuit generates, as long as the control potential indicates that the logical threshold potential is not equal to the reference potential, a substrate potential applied to the semiconductor substrate so that the logical threshold potential is equal to the reference potential, and stops operating after the logical threshold potential becomes equal to the reference potential. A switch circuit breaks a pass-through current path formed in the logical threshold potential output circuit when the control potential indicates that the logical threshold potential becomes equal to the reference potential.