Patents Examined by Kaying Kue
  • Patent number: 10225970
    Abstract: A tape feeder includes a gate, a gate drive mechanism, and a tape feed mechanism. The gate is provided in an insertion port through which a carrier tape storing components is inserted. In the gate drive mechanism, a tape feed mechanism which drives the gate in opening and closing directions feeds the components stored in the inserted carrier tape to a pickup position. The gate drive mechanism includes a spring member which biases the gate in the closing direction, and a solenoid which drives the gate in the opening direction against a biasing force of the spring member.
    Type: Grant
    Filed: March 21, 2016
    Date of Patent: March 5, 2019
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Ryouji Eguchi, Kazunori Kanai, Nobuto Yasuhira, Tatsuo Yamamura, Minoru Kitani, Takashi Tamura
  • Patent number: 10224064
    Abstract: A method involves depositing a near-field transducer on a substrate of a slider. The near-field transducer comprises a plate-like enlarged portion and a peg portion. A first hard stop extending from the near field transducer and an air bearing surface is formed. A heat sink is formed on the enlarged portion and the first hard stop. A dielectric material is deposited over the near-field transducer and the heat sink. A second hard stop is deposited on the dielectric material away from the air bearing surface. The second hard stop comprises a recess corresponding in size and location to the heat sink. The method involves milling at an oblique angle to the substrate between the first hard stop and second hard stop to cut through the heat sink at the angle. The recess of the second hard stop increases a milling rate over the heat sink compared to a second milling rate of the dielectric away from the heat sink.
    Type: Grant
    Filed: January 4, 2016
    Date of Patent: March 5, 2019
    Assignee: Seagate Technology LLC
    Inventors: Anusha Natarajarathinam, Yongjun Zhao, Hui Brickner, Dongsung Hong
  • Patent number: 10219390
    Abstract: A carrier board having two opposite surfaces is provided and a releasing film and a metal layer are formed on the two opposite surfaces respectively. Each metal layer formed with positioning pads is covered with a first hot-melt-dielectric layer where a passive component is disposed. The passive component has upper and lower surfaces each having electrode pads. Each first hot-melt-dielectric layer is disposed on a core board having a cavity to receive the passive component. A second hot-melt-dielectric layer is stacked on each core board. The first and second hot-melt-dielectric layers are heat pressed to form two dielectric layer units each having a top surface and a bottom surface. The carrier board and the releasing films are removed to separate the dielectric layer units. Wiring layers are formed on each top surface and each bottom surface and electrically connected to the electrode pads of the upper and lower surfaces respectively.
    Type: Grant
    Filed: September 14, 2015
    Date of Patent: February 26, 2019
    Assignee: Unimicron Technology Corp.
    Inventors: Shih-Pin Hsu, Zhao-Chong Zeng
  • Patent number: 10210890
    Abstract: A method for producing a wired circuit board includes a first step of preparing a metal supporting layer; a second step of forming an insulating layer having a first opening and terminal forming portions on the metal supporting layer; a third step of forming a conductor layer having terminal portions and an electrically conductive portion on the insulating layer; a fourth step of, by partially removing the metal supporting layer, forming a metal supporting frame portion, a metal supporting connecting portion, and a reinforcement metal supporting portion; and a fifth step of forming a metal plating layer at surfaces of the terminal portions by electrolytic plating via the metal supporting connecting portion.
    Type: Grant
    Filed: March 2, 2016
    Date of Patent: February 19, 2019
    Assignee: NITTO DENKO CORPORATION
    Inventor: Yoshito Fujimura
  • Patent number: 10195726
    Abstract: A de-mating apparatus includes a first component, a second component and a pair of parallel linear bearings. The first component includes a first pair of arms, each of the first pair of arms including a first lift surface. The second component includes a second pair of arms, each of the second pair of arms including a second lift surface. The second lift surfaces are parallel to the first lift surfaces. The linear bearings connect the first component to the second component such that the first pair of arms may move perpendicularly to the first lift surfaces between at least a first position adjacent to the second pair of arms and a second position apart from the second pair of arms to de-mate an electrical connector assembly. A bearing plane defined by the pair of linear bearings does not intersect the first pair of arms.
    Type: Grant
    Filed: March 17, 2016
    Date of Patent: February 5, 2019
    Assignee: Ion Corporation
    Inventors: Chung C. Truong, Thomas P. Jones, II
  • Patent number: 10199153
    Abstract: For producing an inter-layer conductive structure of a circuit board, an insulating layer, a first conductive layer, a second conductive layer and an electric contact material are provided, wherein the insulating layer includes at least a conductive hole therein. The electric contact material is inserted into the conductive hole of the insulating layer to form a conductive plug, and the first and second conductive layers are laminated to opposite surfaces of the insulating layer, respectively. After lamination, the conductive plug has two ends thereof in electric contact with the first conductive layer and the second conductive layer, respectively.
    Type: Grant
    Filed: June 30, 2015
    Date of Patent: February 5, 2019
    Assignee: CYNTEC CO., LTD
    Inventors: Yi-Wei Chen, Cheng-Chang Lee
  • Patent number: 10194537
    Abstract: A printed circuit board and method of manufacturing same, the printed circuit board comprising a stack of layers. The stack of layers being comprised of alternating circuit layers and insulating layers that are laminated together. The stack of layers includes an area with resin cured to a degree. The area has a coefficient of thermal expansion that is dependent, at least in part, on the degree of curing of the resin.
    Type: Grant
    Filed: March 25, 2013
    Date of Patent: January 29, 2019
    Assignee: International Business Machines Corporation
    Inventors: Bruce J. Chamberlin, Joseph Kuczynski, Paula M. Nixa
  • Patent number: 10163742
    Abstract: A method of forming a custom module lid. The method may include placing a multichip module (MCM) between a module base and a temporary lid, target components are exposed through viewing windows in the temporary lid, a top surface of the target components is measured and mapped to create a target profile, the target profile is used to form custom pockets in a custom lid, and the custom pockets correspond to the target components.
    Type: Grant
    Filed: August 25, 2015
    Date of Patent: December 25, 2018
    Assignee: International Business Machines Corporation
    Inventors: Amilcar R. Arvelo, Michael J. Ellsworth, Eric J. McKeever, Thong N. Nguyen, Edward J. Seminaro
  • Patent number: 10145866
    Abstract: A current measurement connector may include a first part and a second part. Each part may include a mount and a joint. The first and second part may be joined via the respective joints through a current transformer interposed between the first and second parts. The respective mounts may be configured to receive a current from a current source and pass the received current through the current transformer via the first and second parts inducing a current in the current transformer. The induced current may be useable to measure the current from the current source. Methods for fabricating the current measurement connector may include die casting the first and second parts and press fitting the first and second parts at the respective joints through the current transformer. Methods for use may include withstanding a fault current pulse and dissipating heat associated with the pulse via the first and second parts.
    Type: Grant
    Filed: September 17, 2015
    Date of Patent: December 4, 2018
    Assignee: NATIONAL INSTRUMENTS CORPORATION
    Inventor: David R. Pasternak
  • Patent number: 10149390
    Abstract: The technology disclosed relates to accommodating embedded substrates during direct writing onto a printed circuit board and to other patterning problems that benefit from an extended depth of focus. In particular, it relates to multi-focus direct writing of a workpiece by the continuous or step-wise movement of the workpiece during the sequence of exposures having different focus planes. In one implementation, a multi-arm rotating direct writer is configured for interleaved writing focused on two or more focal planes that generally correspond to two or more surface heights of a radiation sensitive layer that overlays the uneven workpiece. Alternating arms can produce interleaved writing to the two or more focal planes.
    Type: Grant
    Filed: August 27, 2013
    Date of Patent: December 4, 2018
    Assignee: Mycronic AB
    Inventors: Per Askebjer, Mats Rosling
  • Patent number: 10135214
    Abstract: A line card of a set of line cards is configured to be coupled to a set of switch-fabric cards to collectively define at least a portion of an orthogonal cross fabric without a midplane board. The line card has an edge portion, a first side and a second side, opposite the first side. The line card includes a set of first set of connectors and a second set of connectors. The first set of connectors is disposed along the edge portion on the first side of the line card and the second set of connectors is disposed along the edge portion on the second side of the line card.
    Type: Grant
    Filed: August 31, 2015
    Date of Patent: November 20, 2018
    Assignee: Juniper Networks, Inc.
    Inventors: Boris Reynov, Jack W. Kohn, Ben T. Nitzan, Venkata S. Raju Penmetsa, Oscar Diaz-Landa, Shreeram Siddhaye
  • Patent number: 10123465
    Abstract: A method of forming a power-module assembly includes arranging power stages in a cavity of a container such that the power stages are spaced apart from walls of the container. The method further includes inserting a core between each of the power stages, and installing a manifold on top of the power stages. The method also includes putting resin into the cavity to form a housing of the power-module assembly, and removing the core to reveal coolant chambers between each of the power stages.
    Type: Grant
    Filed: April 15, 2015
    Date of Patent: November 6, 2018
    Assignee: Ford Global Technologies, LLC
    Inventors: Guangyin Lei, Michael W. Degner, Edward Chan-Jiun Jih
  • Patent number: 10114039
    Abstract: This disclosure relates to a method of fabrication contact pins 24 used in testing circuit components, typically integrated circuits and the contact pins themselves. It is desirable to selectively radius certain portions of each pin to achieve desired performance of the entire pin. The portion to be radiused is cut to the desire shaped from a blank material. The portion which is not to be radiused is not cut to its final shape from the blank but to a larger shape which includes the material for the final shape. The entire cut portion is then treated to shape or round all exposed edges. Then the remaining portion of the pin is cut out from the larger blank area which was previously retained, leaving those portions with non-radiused edged.
    Type: Grant
    Filed: April 25, 2016
    Date of Patent: October 30, 2018
    Assignee: Johnstech International Corporation
    Inventors: David Johnson, Michael Andres, Neil Graf, Kenna Pretts
  • Patent number: 10107256
    Abstract: A wye ring centering system is provided. The system includes a plurality of rollers configured for contacting a wye ring, and a plurality of mounting fasteners configured for supporting the plurality of rollers. Each of the mounting fasteners is configured to pass through a fan hub. The plurality of rollers and the plurality of mounting fasteners are distributed at substantially equal intervals around the fan hub. The wye ring is placed over the plurality of rollers to center the wye ring around a shaft.
    Type: Grant
    Filed: February 3, 2016
    Date of Patent: October 23, 2018
    Assignee: GENERAL ELECTRIC COMPANY
    Inventors: Ulrich Werner Neumann, Mark Randall Stewart
  • Patent number: 10074463
    Abstract: A method for making a high-temperature winding cable is winding a tinned copper line around a coaxial line, signal lines and power lines after being assembled together, lapping the rim of the tinned copper line with a packaging material of Polytetrafluoroethene, and then, extruding an insulating layer of thermoplastic material on the rim of the packaging material, and finally, extruding an outer cover of fluororubber on the outer rim of the insulating layer, thereby forming a cable; sintering the cable; winding the sintered cable clockwise around and fixing it to a iron bar; cooling the wound cable; and finally, taking down the wound cable from the iron bar by rewinding it counterclockwise so as to obtain a high-temperature winding cable. The winding cable so made is not melt, damaged, and retains elasticity after the impact of high temperature 260° C.
    Type: Grant
    Filed: December 30, 2015
    Date of Patent: September 11, 2018
    Assignee: VADD TECH INC.
    Inventor: King-Chung Huang
  • Patent number: 10068693
    Abstract: A multi-layer wiring structure includes a first conductive structure, a second conductive structure and an insulating layer. To manufacturing the multi-layer wiring structure, a first conductive structure and a second conductive structure are provided. The first conductive structure and the second conductive structure include a plurality of wiring patterns. Then, the insulating layer is disposed between the first conductive structure and the second conductive structure. The insulting layer is thinner than the first conductive structure or the second conductive structure. The first conductive structure, the insulating layer and the second conductive structure are laminated to form the multi-layer wiring structure. A planar magnetic element having a compact coil manufactured by the method is also provided.
    Type: Grant
    Filed: November 3, 2015
    Date of Patent: September 4, 2018
    Assignee: CYNTEC CO., LTD.
    Inventors: Chun-Chih Lin, Yi-Wei Chen, Yi-Ting Lai, Chu-keng Lin, Cheng-Chang Lee
  • Patent number: 10061093
    Abstract: A method, system, and apparatus are disclosed for a ruggedized photonic crystal (PC) sensor packaging. In particular, the present disclosure teaches a ruggedized packaging for a photonic crystal sensor that includes of a hermetic-seal high-temperature jacket and a ferrule that eliminate the exposure of the optical fiber as well as the critical part of the photonic crystal sensor to harsh environments. The disclosed packaging methods enable photonic crystal based sensors to operate in challenging environments where adverse environmental conditions, such as electromagnetic interference (EMI), corrosive fluids, large temperature variations, and strong mechanical vibrations, currently exclude the use of traditional sensor technologies.
    Type: Grant
    Filed: October 14, 2016
    Date of Patent: August 28, 2018
    Assignee: The Boeing Company
    Inventors: Michael A. Carralero, Eric Y. Chan, Dennis G. Koshinz
  • Patent number: 10056346
    Abstract: A chip attach frame is used to align pins of an integrated circuit chip with pads on a chip carrier. A frame block has a socket defining two alignment edges that form a reference corner. The chip is lowered into the socket, and the chip carrier is inclined while it supports the frame block and chip until the chip moves under force of gravity to the reference corner. Once located at the reference corner, the chip position is carefully adjusted by moving the frame block in the x- and y-directions until the pins are aligned with the pads. The frame block is spring biased against movement in the x- and y-directions, and the position of the frame block is adjusted using thumbscrews. A plunger mechanism can be used to secure the integrated circuit chip in forcible engagement with the chip carrier once the pins are aligned with the pads.
    Type: Grant
    Filed: February 20, 2017
    Date of Patent: August 21, 2018
    Assignee: International Business Machines Corporation
    Inventors: Martin Eckert, Otto Torreiter, Quintino L. Trianni
  • Patent number: 10057983
    Abstract: A method may involve: forming a first bio-compatible layer; forming an etch stop over a portion of the first bio-compatible layer; forming a conductive pattern over the etch stop and the first bio-compatible layer, wherein the conductive pattern defines an antenna, sensor electrodes, electrical contacts, and one or more electrical interconnects; mounting an electronic component to the electrical contacts; forming a second bio-compatible layer over the electronic component, the antenna, the sensor electrodes, the electrical contacts, the one or more electrical interconnects, and the etch stop; and etching, using an etchant, a portion of the second bio-compatible layer to form an opening in the second bio-compatible layer and thereby expose the sensor electrodes, wherein the etch stop inhibits etching of the portion of the first bio-compatible layer by the etchant.
    Type: Grant
    Filed: June 13, 2014
    Date of Patent: August 21, 2018
    Assignee: Verily Life Sciences LLC
    Inventors: James Etzkorn, Harvey Ho
  • Patent number: 10028394
    Abstract: This disclosure relates generally to an electronic chip package that can include a die and a buildup layer substantially enveloping the die. Electrical interconnects can be electrically coupled to the die and passing, at least in part, through the buildup layer. An optical emitter can be electrically coupled to the die with a first one of the electrical interconnects and configured to emit light from a first major surface of the electronic chip package. A solder bump can be electrically coupled to the die with a second one of the electrical interconnects and positioned on a second major surface of the electronic chip package different from the first major surface.
    Type: Grant
    Filed: December 17, 2012
    Date of Patent: July 17, 2018
    Assignee: Intel Corporation
    Inventors: Mihir K Roy, Matthew J Manusharow