Abstract: Circuits and methods for improving the noise figure (NF) of an amplifier, particularly an LNA, in high-gain modes while improving the IIP3 of the amplifier in low-gain modes. The source of an amplifier common-source FET is coupled to circuit ground thorough a degeneration circuit comprising a two-port inductor and a bypass switch coupled in parallel with the inductor. A switched feedback circuit is coupled between the gate of the common-source FET and a feedback node in the amplifier output signal path. During a low gain mode, the inductor is entirely bypassed and the enabled feedback circuit lowers the input impedance of the common-source FET and reduces the gain of the amplifier circuit, essentially eliminating the need for a degeneration inductor. During a high gain mode, the source of the common-source FET is coupled to circuit ground through the inductor and the feedback circuit is disabled. Other gain modes are supported.

Abstract: A power amplifier circuit includes a first impedance transformer circuit arranged to connect with a carrier device, and a second impedance transformer circuit arranged to connect with a peaking device. Both the first and the second impedance transformer circuit include a parallel impedance transformer arrangement.

Abstract: A bonded structure is disclosed. The bonded structure can include a semiconductor element comprising active circuitry and a first bonding layer. The bonded structure can include a protective element directly bonded to the semiconductor element without an adhesive along a bonding interface. The protective element can include an obstructive material disposed over the active circuitry and a second bonding layer on the obstructive material. The second bonding layer can be directly bonded to the first bonding layer without an adhesive. The obstructive material can be configured to obstruct external access to the active circuitry.

Abstract: An automatic gain control circuit includes a linear-to-log conversion circuit, a current amplifier circuit, and an amplitude sense circuit. The current amplifier circuit includes a current input terminal coupled to an output terminal of the linear-to-log conversion circuit. The amplitude sense circuit includes an input terminal coupled to an output terminal of the current amplifier circuit, and an output terminal coupled to a gain control input terminal of the current amplifier circuit.

Abstract: To provide a semiconductor device that makes it possible to reduce a cell circuit area and an increase in resolution. There is provided a semiconductor device including: a first region in which readout cells are arranged in an array form, the readout cells having one of input transistors included in a differential amplifier: and a second region in which reference cells are arranged in an array form, the reference cells having another input transistor included in the differential amplifier, the first region and the second region being separated from each other.

Abstract: Circuits and methods for achieving good amplifier AM-AM and AM-PM metrics while achieving good power, PAE, linearity, and EVM performance. Embodiments compensate for a non-linear distortion profile (e.g., an AM-PM and/or AM-AM profile) in an amplifier by pre-processing an input signal, such as a radio-frequency signal, to alter the non-linear distortion profile of the input signal so as to compensate for the non-linear distortion profile imposed by a coupled device, such as an amplifier.

Abstract: A Doherty power amplifier circuit having a main power amplification device, an auxiliary power amplification device arranged in parallel with the main power amplification device, and a load modulation circuit comprising a harmonic injection circuit connected with respective outputs of the main power amplification device and the auxiliary power amplification device. The harmonic injection circuit is arranged to transfer harmonic components generated at the main power amplification device to the auxiliary power amplification device and harmonic components generated at the auxiliary power amplification device to the main power amplification device, when both the main and auxiliary power amplification devices are operating, for modulating the respective outputs of the main power amplification device and the auxiliary power amplification device.

Abstract: Disclosed is an embedded multi-die interconnect bridge (EMIB) substrate. The EMIB substrate can comprise an organic substrate, a bridge embedded in the organic substrate and a plurality of routing layers. The plurality of routing layers can be embedded within the bridge. Each routing layer can have a plurality of traces. Each of the plurality of routing layers can have a coefficient of thermal expansion (CTE) that varies from an adjacent routing layer.

Abstract: CRLH lines including left-handed shunt inductors and left-handed series capacitors are provided on gate side transmission lines of a plurality of FETs.

Abstract: A semiconductor package and a method of forming the semiconductor package are provided. The method includes providing a first substrate, forming a wiring structure containing at least two first wiring layers, disposing a first insulating layer between adjacent two first wiring layers, and patterning the first insulating layer to form a plurality of first through-holes. The adjacent two first wiring layers are electrically connected to each other through the plurality of first through-holes. The method also includes providing at least one semiconductor element each including a plurality of pins. In addition, the method includes disposing the plurality of pins of the each semiconductor element on a side of the wiring structure away from the first substrate. Further, the method includes encapsulating the at least one semiconductor element, and placing a ball on a side of the wiring structure away from the at least one semiconductor element.

Abstract: An operational amplifier includes a first differential input pair, a first switch and a second switch. The first differential input pair includes a first input transistor and a second input transistor. The first input transistor has a gate terminal coupled to an output terminal of the operational amplifier. The second input transistor has a gate terminal. The first switch is coupled between the gate terminal of the first input transistor and the gate terminal of the second input transistor. The second switch is coupled between a first input terminal of the operational amplifier and the gate terminal of the second input transistor.

Abstract: The semiconductor device includes: a heat spreader; a semiconductor element joined to the heat spreader via a first joining member; a first lead frame joined to the heat spreader via a second joining member; a second lead frame joined to the semiconductor element via a third joining member; and a mold resin. In a cross-sectional shape obtained by cutting at a plane perpendicular to a one-side surface of the heat spreader, an angle on the third joining member side out of two angles formed by a one-side surface of the semiconductor element and a straight line connecting an end point of a joining surface between the third joining member and the semiconductor element and an end point of a joining surface between the third joining member and the second lead frame, is not smaller than 90° and not larger than 135°.

Abstract: A semiconductor device includes a substrate including a first active region, a second active region and a field region between the first and second active regions, and a gate structure formed on the substrate to cross the first active region, the second active region and the field region. The gate structure includes a p type metal gate electrode and an n-type metal gate electrode directly contacting each other, the p-type metal gate electrode extends from the first active region less than half way toward the second active region.

Abstract: According to one embodiment, a semiconductor device includes the following configuration. A detection circuit detects a state of a clock signal. An amplification circuit changes a gain based on the state of the clock signal detected by the detection circuit. An amplification circuit amplifies a first voltage with the gain and outputs a second voltage obtained as a result of amplification. A conversion circuit converts the second voltage output from the amplification circuit to first data. An isolation circuit includes a driver and a receiver electrically isolated from the driver. The driver transmits a signal corresponding to the first data to the receiver. The receiver outputs second data corresponding to the signal transmitted from the driver. The output circuit outputs the second data output from the isolation circuit.

Abstract: A signal gain determination circuit including a digital comparator, a digital controller and an arithmetic module, and a signal gain determination method are provided. A sensing integration circuit generates a first count during a first integration time according to a first sensing signal. The digital comparator compares the first count and a predetermined count to generate a comparison result. The digital controller generates a control signal for indicating a signal gain to a signal amplifier of the sensing integration circuit according to the comparison result. The signal amplifier adjusts the first sensing signal according to the signal gain to generate a second sensing signal, so that the sensing integration circuit generates a second count corresponding to the second sensing signal during a second integration time. The arithmetic module generates an output count corresponding to the first sensing signal according to the second count and the signal gain.

Abstract: Transconductor circuits with programmable tradeoff between bandwidth and flicker noise are disclosed. An example circuit includes an input port, an output port, a plurality of transistors, and a switch arrangement that includes a plurality of switches, configured to change coupling between the input port, the output port, and the transistors to place the transconductor circuit in a first or a second mode of operation. An input capacitance of the transconductor circuit operating in the first mode is larger than when the transconductor circuit is operating in the second mode. In the first mode, having a larger input capacitance results in a decreased flicker noise because the amount of flicker noise is inversely proportional to the input capacitance. In the second mode, having a smaller input capacitance leads to an increased flicker noise but that is acceptable for wide-bandwidth applications because wide-bandwidth signals may be less sensitive to flicker noise.

Abstract: A power amplifier circuit includes an amplifier transistor having a base, a collector, a bias circuit, and a first resistance element connected between the base of the amplifier transistor and the bias circuit. The bias circuit includes a voltage generation circuit, a first transistor having a base to which a first direct-current voltage is supplied, and an emitter from which the bias current or voltage is supplied, a second transistor having a base to which a second direct-current voltage is supplied, and an emitter connected to the emitter of the first transistor, a signal supply circuit disposed between the base of the amplifier transistor and the base of the second transistor, and an impedance circuit disposed between the base of the first transistor and the base of the second transistor.

Abstract: Some embodiments include an integrated structure having vertically-stacked conductive levels. Upper conductive levels are memory cell levels, and a lower conductive level is a select device level. Conductively-doped semiconductor material is under the select device level. Channel material extends along the memory cell levels and the select device level, and extends into the conductively-doped semiconductor material. A region of the channel material that extends into the conductively-doped semiconductor material is a lower region of the channel material and has a vertical sidewall. Tunneling material, charge-storage material and charge-blocking material extend along the channel material and are between the channel material and the conductive levels. The tunneling material, charge-storage material and charge-blocking material are not along at least a portion of the vertical sidewall of the lower region of the channel material, and the conductively-doped semiconductor material is directly against such portion.

Abstract: A package structure, including a redistribution circuit layer, a first die, a dielectric body, a first connection circuit, a patterned insulating layer, a second die and a third die, is provided. The first die is disposed on the redistribution circuit layer and is electrically connected to the redistribution circuit layer. The dielectric body is disposed on the redistribution circuit layer and covers the first die. The first connection circuit is disposed on the dielectric body and is electrically connected to the redistribution circuit layer. The patterned insulating layer covers the first connection circuit. A portion of the patterned insulating layer is embedded in the dielectric body. The second die is disposed on the dielectric body and is electrically connected to the first connection circuit. The third die is disposed on the redistribution circuit layer, is opposite to the first die, and is electrically connected to the redistribution circuit layer.

Abstract: Provided is a power amplification module that includes: a first transistor, a first signal being inputted to a base thereof; a second transistor, the first signal being inputted to a base thereof and a collector thereof being connected to a collector of the first transistor; a first resistor, a first bias current being supplied to one end thereof and another end thereof being connected to the base of the first transistor; a second resistor, one end thereof being connected to the one end of the first resistor and another end thereof being connected to the base of the second transistor; and a third resistor, a second bias current being supplied to one end thereof and another end thereof being connected to the base of the second transistor.