Abstract: A semiconductor package structure and a method for manufacturing a semiconductor package structure are provided. The package structure includes an outer lead portion, an inner lead portion, an encapsulant, and a first conductive layer. The outer lead portion has a first surface and a second surface opposite to the first surface. The inner lead portion is connected to the outer lead portion. The inner lead portion has a first surface and a second surface opposite to the first surface. The encapsulant covers the first surface of the outer lead portion and the first surface of the inner lead portion. The second surface of the outer lead portion and the second surface of the inner lead portion are substantially coplanar and are recessed from a surface of the encapsulant. The first conductive layer is disposed on the second surface of the outer lead portion.

Abstract: A chip package structure includes at least one chip, at least one thermally conductive element, a molding compound, and a redistribution layer. The respective chip has an active surface and a back surface opposite to each other and a plurality of electrodes disposed on the active surface. The thermally conductive element is disposed on the back surface of the respective chip. The molding compound encapsulates the chip and the thermally conductive element and has an upper surface and a lower surface opposite to each other. A bottom surface of each of the electrodes of the respective chip is aligned with the lower surface of the molding compound. The molding compound exposes a top surface of the respective thermally conductive element. The redistribution layer is disposed on the lower surface of the molding compound and electrically connected to the electrodes of the respective chip.

Abstract: A semiconductor package includes a molding compound, a chip and a conductive pad, wherein the chip is electrically connected to the conductive pad and both are encapsulated in the molding compound. An anchor flange is formed around a top surface of the conductive pad by over plating. When the conductive pad is embedded in the molding compound, the anchor flange engages the molding compound to prevent the conductive pad from separation. Bottoms of a chip and the conductive pad are exposed from the molding compound for electrically soldering to a circuit board.

Abstract: Embodiments of methods for forming contact structures and semiconductor devices thereof are disclosed. In an example, a semiconductor device includes an insulating layer, a conductive layer over the insulating layer, and a spacer structure in the conductive layer and in contact with the insulating layer. The semiconductor device also includes a first contact structure in the spacer structure and extending vertically through the insulating layer. The first contact structure includes a first contact portion and a second contact portion in contact with each other. An upper surface of the second contact portion is coplanar with an upper surface of the conductive layer.

Abstract: A power amplifier circuit includes a current generator and a current mirror driver. The current generator has a first input connected to a first voltage supply and an output configured to generate a first current. The current generator includes a first transistor, a second transistor, a first resistor and a second resistor. The first transistor has an emitter connected to ground. The second transistor has a base connected to a base of the first transistor and an emitter connected to ground. The first resistor is connected between the first voltage supply and a collector of the first transistor. The second resistor is connected between the first voltage supply and a collector of the second transistor. The current mirror drive has a first input connected to the output of the current generator to receive the first current and an output configured to generate a second current.

Abstract: Enhanced operational amplifier trim circuitry and techniques are presented herein. In one implementation, a circuit includes a reference circuit configured to produce a set of reference voltages, and a digital-to-analog conversion (DAC) circuit. The DAC circuit comprises a plurality of transistor pairs, where each pair among the plurality of transistor pairs is configured to provide portions of adjustment currents for an operational amplifier based at least on the set of reference voltages and sizing among transistors of each pair. The circuit also includes drain switching elements coupled to drain terminals of the transistors of each pair and configured to selectively couple one or more of the portions of the adjustment currents to the operational amplifier in accordance with digital trim codes.

Abstract: An operational amplifier includes a differential amplifier circuit and a common mode feedback circuit. The differential amplifier circuit includes a bias circuit, an amplifier circuit, and a load circuit. The bias circuit generates a first operation voltage. The amplifier circuit receives a pair of input signals, and generates a pair of output signals according to the input signals and the first operation voltage. The load circuit is coupled to the amplifier circuit. The common mode feedback circuit generates at least one common mode feedback voltage based on a common mode voltage and a reference voltage. The common mode voltage is associated with the output signals. The at least one common mode feedback voltage is for controlling the bias circuit and the load circuit, to control a direct current (DC) voltage level of the differential amplifier circuit.

Abstract: In one embodiment, stable and controlled circuit element biasing is provided in a circuit comprising a voltage source operable to output a first voltage, a reference voltage source operable to output a reference voltage, a circuit element biased, during operation, by the first voltage at a first end and by a second voltage at a second end, a voltage controller coupled to the second end of the circuit element, wherein the voltage controller is operable to adjust the second voltage based on a gain output, a gain controller operable to receive the reference voltage as a first input and the second voltage as a second input, wherein the gain controller is operable to generate, at an output of the gain controller, the gain output based on the second voltage and the reference voltage, and a feedback loop that extends from the output of the gain controller, through the voltage controller, and to the second input.

Abstract: Balun device and differential phase shifter are provided. The balun device includes a first primary coil, a first secondary coil, a second primary coil and a second secondary coil, the first primary coil having a first terminal receiving a first differential signal, and a second terminal outputting a first in-phase component, the first secondary coil having a first terminal outputting a first component orthogonal to the first in-phase component, and a second terminal coupled to AC ground, the second primary coil having a first terminal receiving a second differential signal, and a second terminal outputting a second in-phase component; the second secondary coil having a first terminal outputting a second component orthogonal to the second in-phase component, and a second terminal coupled to AC ground; phase differences between the first and second differential signals, between the first and second in-phase components, between the first and second orthogonal component are 180°.

Abstract: Methods, apparatus, and systems are disclosed that adjust transient response in a multistage system. An example apparatus includes a first filter including an input configured to be coupled to an output of a master stage, an amplifier, the first input of the amplifier coupled to the input of the first filter, the second input of the amplifier coupled to the output of the first filter, a second filter, the input of the second filter coupled to the output of the amplifier, and a comparator, the first input of the comparator coupled to the input of the first filter circuit, the second input of the comparator coupled to the output of the amplifier, the third input of the comparator coupled to the output of the second filter, and the output of the comparator adapted to be coupled to a latch.

Abstract: Techniques for biasing output transistor of a push-pull amplifier output stage are provided. In certain applications the techniques can improve efficiency of the amplifier. In an example, a circuit can include an output stage including first and second output transistors, a first scaled replica transistor corresponding to the first output transistor, and an amplifier circuit in a feedback arrangement for biasing a gate of the first output transistor at a level that, at a specified stand-by current level of the first output transistor, reproduces a voltage difference between the drain and source terminals of the first output transistor across the drain and source terminals of the first replica transistor.

Abstract: A microelectronic device comprises a first die and a second die attached to the first die. The first die comprises a memory array region comprising a stack structure comprising vertically alternating conductive structures and insulative structures, vertically extending strings of memory cells within the stack structure, and first bond pad structures vertically neighboring the vertically extending strings of memory cells. The second die comprises a control logic region comprising control logic devices configured to effectuate at least a portion of control operations for the vertically extending string of memory cells, second bond pad structures in electrical communication with the first bond pad structures, and signal routing structures located at an interface between the first die and the second die. Related microelectronic devices, electronic systems, and methods are also described.

Abstract: Power amplification system with adjustable common base bias. A power amplification system can include a cascode amplifier coupled to a radio-frequency input signal and coupled to a radio-frequency output. The power amplification system can further include a biasing component configured to apply one or more biasing signals to the cascode amplifier, the biasing component including a bias controller and one or more bias components. Each respective bias component may be coupled to a respective bias transistor.

Abstract: A dual-mode average power tracking (APT) controller operates in a first mode to move the control voltage quickly without concern for ripple or ringing. When this coarse adjustment takes the control voltage to within a desired margin of a target, the controller may switch to a second mode, where the APT controller more slowly approaches the target, but has reduced ringing or ripples. The mode is changed by changing resistance and capacitance values in a loop filter within the APT circuit. In a further aspect, a pulse shaper circuit may inject a pulse to force the control voltage to change more rapidly. By switching modes in this fashion, the control voltage may quickly reach a desired target, and then remain in the second mode during a transmission time slot such that the control voltage is clean throughout.

Abstract: In a RC-IGBT chip, an anode electrode film and an emitter electrode film are arranged with a distance therebetween. The anode electrode film and the emitter electrode film are electrically connected by a wiring conductor having an external impedance and an external impedance. The external impedance and the external impedance include the resistance of the wiring conductor and the inductance of the wiring conductor.

Abstract: A semiconductor package includes a first semiconductor die, a molded die, a third encapsulant, and a redistribution structure. The molded die includes a chip, a first encapsulant, and a second encapsulant. The first encapsulant laterally wraps the chip. The second encapsulant laterally wraps the first encapsulant. The third encapsulant laterally wraps the first semiconductor die and the molded die. The redistribution structure extends on the second encapsulant, the third encapsulant, and the first semiconductor die. The redistribution structure is electrically connected to the first semiconductor die and the molded die. The second encapsulant separates the first encapsulant from the third encapsulant.

Abstract: A memory device is disclosed. The disclosed memory device may include a first wafer, and a second wafer stacked on and bonded to the first wafer. The first wafer may include a cell structure including a memory cell array; and a first logic structure disposed under the cell structure, and including a column control circuit. The second wafer may include a second logic structure including a row control circuit.

Abstract: An RF transceiver front end includes a receiver limb including a length of transmission line, an impedance matching network, a downstream shunt switch and a downstream further receiver component and a transmitter limb. The impedance matching network is configured to transform the input impedance of the further receiver component to match the input impedance of the receiver limb when the shunt switch is open and the RF transceiver front end is operable in receiver mode. The impedance matching network is further configured to transform the input impedance of the shunt switch to present an open circuit as the input impedance of the receiver limb when the shunt switch is closed and the RF transceiver front end is operable in transmitter mode. The length of transmission line can be from zero to less than ?/4 at the operating frequency of the RF transceiver.

Abstract: Some embodiments relate to an integrated chip that includes a first source/drain region and a second source/drain region disposed in a substrate. A plane that is substantially perpendicular to an upper surface of the substrate traverses the first source/drain region and the second source/drain region. Agate electrode extends over a channel region in the substrate between the first source/drain region and the second source/drain region. The gate electrode is separated from the channel region by way of a charge trapping dielectric structure. The charge trapping dielectric structure includes a tunnel dielectric layer, a charge trapping dielectric layer over the tunnel dielectric layer, and a blocking dielectric layer over the charge trapping dielectric layer. The channel region has a channel width measured perpendicularly to the plane, and the tunnel dielectric layer has different thicknesses at different respective points along the channel width.

Abstract: A circuit is disclosed, in accordance with some embodiments. The circuit includes a transistor stage, a resistive element, a first tunable capacitive element and a second tunable capacitive element. The transistor stage includes a first input/output terminal and a second input/output terminal. The resistive element is connected to the transistor stage. The first tunable capacitive element is connected in parallel with the resistive element. The second tunable capacitive element is connected to the second input/output terminal of the transistor stage.