Patents Examined by Michael Trinh
  • Patent number: 8546177
    Abstract: Methods of manufacturing a phase-change memory device and a semiconductor device are provided. The method of manufacturing the phase-change memory device includes forming a switching device layer, an ohmic contact layer, and a hard mask layer on a semiconductor substrate, patterning the hard mask layer to form a hard mask pattern, etching the ohmic layer and the switching layer using the hard mask pattern to form a pattern structure including an ohmic contact pattern, a switching device pattern, and the hard mask pattern, selectively oxidizing a surface of the pattern structure, forming an insulating layer to bury the pattern structure, and selectively removing the hard mask pattern other than the oxidized surface thereof to form a contact hole.
    Type: Grant
    Filed: December 29, 2011
    Date of Patent: October 1, 2013
    Assignee: Hynix Semiconductor Inc.
    Inventors: Hye Jin Seo, Keum Bum Lee
  • Patent number: 8546273
    Abstract: Methods and apparatus for forming nitrogen-containing layers are provided herein. In some embodiments, a method of forming a nitrogen-containing layer may include placing a substrate having a first layer disposed thereon on a substrate support of a process chamber; heating the substrate to a temperature of at least about 250 degrees Celsius; and exposing the first layer to a radio frequency (RF) plasma formed from a process gas consisting essentially of ammonia (NH3) and an inert gas while maintaining the process chamber at a pressure of about 10 mTorr to about 40 mTorr to transform at least an upper portion of the first layer into a nitrogen-containing layer.
    Type: Grant
    Filed: July 27, 2011
    Date of Patent: October 1, 2013
    Assignee: Applied Materials, Inc.
    Inventors: Malcolm J. Bevan, Johanes Swenberg, Son T. Nguyen, Wei Liu, Jose Antonio Marin, Jian Li
  • Patent number: 8541307
    Abstract: A treatment method for reducing particles in a Dual Damascene Silicon Nitride (DDSN) process, including the following steps: forming a seed layer of copper on a silicon wafer; depositing a deposition layer of copper to cover the seed layer of copper; planarizing the deposition layer of copper; providing the silicon wafer into a reaction chamber and performing a pre-treatment on a surface of the deposition layer of copper using NH3 gas under a plasma condition so as to reduce copper oxide (CuO) to copper (Cu) formed on the deposition layer of copper; in the reaction chamber, generating an etching block layer on the deposition layer of copper using a DDSN deposition process; cleaning the reaction chamber using NF3 gas; and directing N2O gas into the reaction chamber and removing the remaining hydrogen (H) and fluorine (F) in the reaction chamber using the N2O gas under the plasma condition.
    Type: Grant
    Filed: December 29, 2011
    Date of Patent: September 24, 2013
    Assignee: Shanghai Huali Microelectronics Corporation
    Inventors: Meimei Gu, Duoyuan Hou, Jun Xu, Ke Wang
  • Patent number: 8524554
    Abstract: A dual work function semiconductor device and method for fabricating the same are disclosed. In one aspect, a device includes a first and second transistor on a first and second substrate region. The first and second transistors include a first gate stack having a first work function and a second gate stack having a second work function respectively. The first and second gate stack each include a host dielectric, a gate electrode comprising a metal layer, and a second dielectric capping layer therebetween. The second gate stack further has a first dielectric capping layer between the host dielectric and metal layer. The metal layer is selected to determine the first work function. The first dielectric capping layer is selected to determine the second work function.
    Type: Grant
    Filed: October 16, 2012
    Date of Patent: September 3, 2013
    Assignees: IMEC, Samsung Electronics Co., Ltd., Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Hag-Ju Cho, Anabela Veloso, HongYu Yu, Stefan Kubicek, Shou-Zen Chang
  • Patent number: 8513056
    Abstract: Provided is a semiconductor device and method of fabricating the semiconductor memory device. The semiconductor device may be formed by forming a first welding groove along outside edges of one case of a pair of upper and lower cases, forming a first welding protrusion along outside edges of the other case, the first welding protrusion being formed to correspond to the first welding groove and having a volume larger than a volume of the first welding groove. The method may further include inserting the first welding protrusion into the first welding groove to enclose a memory module in an inner accommodating space of the upper and lower cases, melting the first welding protrusion so that a first portion of the first welding protrusion fills the first welding groove and a second portion of the first welding protrusion fills a space between welding portions of the upper case and the lower case, and solidifying the first and second portions of the first welding protrusion.
    Type: Grant
    Filed: February 26, 2010
    Date of Patent: August 20, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Jae-Hwan Han
  • Patent number: 8507936
    Abstract: An image sensing device for receiving an incident light having an incident angle and photo signals formed thereby is provided. The image sensing device includes a micro prism and a micro lens for adjusting the incident angle and converging the incident light, respectively, a photo sensor for converting the photo signals into electronic signals, and an IC stacking layer for processing the electronic signals.
    Type: Grant
    Filed: February 14, 2012
    Date of Patent: August 13, 2013
    Assignees: Visera Technologies Company Ltd., Omnivision Technologies Inc.
    Inventor: Hsiao-Wen Lee
  • Patent number: 8507301
    Abstract: A TFT array substrate includes: a gate electrode connected to a gate line; a source electrode connected to a data line crossing the gate line to define a pixel region; a drain electrode which is opposite to the source electrode with a channel in between; a semiconductor layer defining the channel between the source electrode and the drain electrode; a pixel electrode in the pixel region and connected to the drain electrode; a channel passivation layer on the channel of the semiconductor layer; a gate pad extending from the gate line, where a semiconductor pattern and a transparent conductive pattern are formed; a data pad connected to the data line, where the transparent conductive pattern is formed; and a gate insulating layer formed under the semiconductor layer, the gate line and the gate pad, and the data line and the data pad.
    Type: Grant
    Filed: November 25, 2009
    Date of Patent: August 13, 2013
    Assignee: LG Display Co., Ltd.
    Inventors: Young Seok Choi, Hong Woo Yu, Ki Sul Cho, Jae Ow Lee, Bo Kyoung Jung
  • Patent number: 8501557
    Abstract: A method of manufacturing a nitride semiconductor device including: forming a nitride semiconductor layer over a substrate wherein the nitride semiconductor layer has a 2DEG channel inside; forming a drain electrode in ohmic contact with the nitride semiconductor layer and a source electrode spaced apart from the drain electrode, in Schottky contact with the nitride semiconductor layer, wherein the source electrode has an ohmic pattern in ohmic contact with the nitride semiconductor layer inside; forming a dielectric layer on the nitride semiconductor layer between the drain electrode and the source electrode and on at least a portion of the source electrode; and forming a gate electrode on the dielectric layer to be spaced apart from the drain electrode, wherein a portion of the gate electrode is formed on the dielectric layer over a drain-side edge portion of the source electrode.
    Type: Grant
    Filed: January 30, 2013
    Date of Patent: August 6, 2013
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Woo Chul Jeon, Ki Yeol Park, Young Hwan Park
  • Patent number: 8501532
    Abstract: An organic light emitting diode display and a fabrication method thereof, the display including a substrate; a thin film transistor on the substrate; and an organic light emitting diode on the substrate, the organic light emitting diode including a pixel electrode, an organic emission layer, and a common electrode, wherein the organic emission layer includes a red (R) pixel, a green (G) pixel, and a blue (B) pixel, the pixel electrode includes a first pixel electrode, a second pixel electrode, and a third pixel electrode that respectively correspond to the red pixel, the green pixel, and the blue pixel, the first pixel electrode, the second pixel electrode, and the third pixel electrode each have different thicknesses, and the first pixel electrode, the second pixel electrode, and the third pixel electrode each include a first hydrophobic layer.
    Type: Grant
    Filed: November 21, 2012
    Date of Patent: August 6, 2013
    Assignee: Samsung Display Co., Ltd.
    Inventors: Beung-Hwa Jeong, Kwang-Nam Kim, Young-Ro Jung, Yun-Sik Ham
  • Patent number: 8501502
    Abstract: Disclosed is a package method for electronic components by a thin substrate, comprising: providing a carrier; forming at least one metal layer and at least one dielectric layer on the carrier for manufacturing the thin substrate, and the thin substrate comprises at least one package unit for connecting at least one chip; forming at least one pad layer on a surface of the thin substrate; parting the thin substrate from the carrier; performing test to the thin substrate to weed out the package unit with defects in the at least one package unit and select the package units for connecting the chips; connecting the chips with the selected package units by flip chip bonding respectively. Accordingly, the yield of the entire package process can be improved and the pointless manufacture material cost can be reduced.
    Type: Grant
    Filed: November 1, 2012
    Date of Patent: August 6, 2013
    Assignee: Princo Middle East FZE
    Inventors: Yeong-yan Guu, Ying-jer Shih
  • Patent number: 8497153
    Abstract: A process for making a back-contact solar cell module is provided. Electrically conductive wires of an integrated back-sheet are physically and electrically attached to the back contacts of the solar cells of a solar cell array through openings in a polymeric interlayer dielectric layer using an electrically conductive binder before thermal lamination of the module.
    Type: Grant
    Filed: October 26, 2012
    Date of Patent: July 30, 2013
    Assignee: E I du Pont de Nemours and Company
    Inventors: Thomas D. Lantzer, Dilip Natarajan, Steven Alcus Threefoot
  • Patent number: 8494207
    Abstract: Improved approaches for providing a speaker within a housing of a portable electronic device are disclosed. The housing of the portable electronic device can be compact, such as a low profile housing. In one embodiment, an acoustic chamber for a speaker can be formed internal to a housing for a portable electronic device using non-dedicated space. In another embodiment, irregular surfaces can be sealed so that an acoustic chamber for a speaker can be formed internal to a housing for a portable electronic device.
    Type: Grant
    Filed: August 9, 2012
    Date of Patent: July 23, 2013
    Assignee: Apple Inc.
    Inventors: Gloria Lin, Derek B. Barrentine, Michael Rosenblatt
  • Patent number: 8492269
    Abstract: In sophisticated semiconductor devices, superior contact resistivity may be accomplished for a given contact configuration by providing hybrid contact elements, at least a portion of which may be comprised of a highly conductive material, such as copper. To this end, a well-established contact material, such as tungsten, may be used as buffer material in order to preserve integrity of sensitive device areas upon depositing the highly conductive metal.
    Type: Grant
    Filed: September 16, 2011
    Date of Patent: July 23, 2013
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Jens Heinrich, Ralf Richter, Torsten Huisinga, Kai Frohberg
  • Patent number: 8487207
    Abstract: A rotatable workpiece holder for holding a hollow cylindrical workpiece thereon functions as a chiller for cooling the hollow cylindrical workpiece. A coolant, e.g., water, is supplied to the hollow cylindrical workpiece through second coolant passages and branch passageways defined in the workpiece holder, thereby cooling the hollow cylindrical workpiece. The coolant forms a film in a clearance between the outer surface of an annular side wall of the workpiece holder and the inner circumferential surface of the hollow cylindrical workpiece.
    Type: Grant
    Filed: January 13, 2010
    Date of Patent: July 16, 2013
    Assignee: Honda Motor Co., Ltd.
    Inventors: Katsuyuki Nakajima, Daisuke Koshino, Akihiro Nemoto
  • Patent number: 8481433
    Abstract: Methods and apparatus for forming nitrogen-containing layers are provided herein. In some embodiments, a method includes placing a substrate having a first layer disposed thereon on a substrate support of a process chamber; heating the substrate to a temperature of at least about 250 degrees Celsius; and exposing the first layer to a radio frequency (RF) plasma formed from a process gas comprising nitrogen while maintaining the process chamber at a pressure of about 10 mTorr to about 40 mTorr to transform at least an upper portion of the first layer into a nitrogen-containing layer. In some embodiments, the process gas includes ammonia (NH3).
    Type: Grant
    Filed: March 29, 2010
    Date of Patent: July 9, 2013
    Assignee: Applied Materials, Inc.
    Inventors: Malcolm J. Bevan, Johanes Swenberg, Son T. Nguyen, Wei Liu, Jose Antonio Marin, Jian Li
  • Patent number: 8470671
    Abstract: A novel method for manufacturing a 3-D vertical memory comprising the steps of dividing a multilayer structure composed of insulating intermediate layers and sacrificial intermediate layers into a first multilayer structure and a second multilayer structure, replacing the sacrificial intermediate layers in the multilayer structures with metal intermediate layers, and manufacturing the channel structure in two multilayer structures.
    Type: Grant
    Filed: October 24, 2012
    Date of Patent: June 25, 2013
    Assignee: Powerchip Technology Corporation
    Inventors: Chao-Wei Lin, Hui-Huang Chen, Chih-Yuan Chen
  • Patent number: 8461478
    Abstract: A system and method for precision cutting using multiple laser beams is described, The system and method includes a combination of optical components that split the output of a single laser into multiple beams, with the power, polarization status and spot size of each split beam being individually controllable, while providing a circularly polarized beam at the surface of a work piece to be cut by the laser beam. A system and method for tracking manufacture of individual stents is also provided.
    Type: Grant
    Filed: February 3, 2010
    Date of Patent: June 11, 2013
    Assignee: Abbott Cardiovascular Systems, Inc.
    Inventors: Li Chen, Randolf Von Oepen
  • Patent number: 8461001
    Abstract: A method to manufacture a trenched semiconductor power device including a plurality of trenched gates surrounded by source regions near a top surface of a semiconductor substrate encompassed in body regions. The method for manufacturing the trenched semiconductor power device includes a step of carrying out a tilt-angle implantation through sidewalls of trenches to form drift regions surrounding the trenches at a lower portion of the body regions with higher doping concentration than the epi layer for Rds reduction, and preventing a degraded breakdown voltage due to a thick oxide in lower portion of trench sidewall and bottom. In an exemplary embodiment, the step of carrying out the tilt-angle implantation through the sidewalls of the trenches further includes a step of carrying out a tilt angle implantation with a tilt-angle ranging between 4 to 30 degrees.
    Type: Grant
    Filed: December 9, 2009
    Date of Patent: June 11, 2013
    Assignee: Force-MOS Technology Corporation
    Inventor: Fwu-Iuan Hshieh
  • Patent number: 8450721
    Abstract: A III-nitride semiconductor device which includes a barrier body between the gate electrode and the gate dielectric thereof.
    Type: Grant
    Filed: June 14, 2011
    Date of Patent: May 28, 2013
    Assignee: International Rectifier Corporation
    Inventors: Robert Beach, Zhi He, Jianjun Cao
  • Patent number: 8440487
    Abstract: The present disclosure provides methods for manufacturing a radio frequency (RF) powder including a plurality of RF particles, each of which includes a circuit element. A plurality of circuit elements, each corresponding to a different RF particle, may be formed on a first surface of a substrate. Grooves may be etched into the first surface of the substrate between the plurality of circuit elements. A protection film may be formed on each of the plurality of circuit elements and a portion of the substrate between a second, opposite surface of the substrate and bottoms of the grooves may be removed so that each of the plurality of circuit elements is associated with the remaining portion of the substrate.
    Type: Grant
    Filed: February 24, 2012
    Date of Patent: May 14, 2013
    Assignee: Philtech Inc.
    Inventor: Yuji Furumura