Abstract: A donor substrate may include a base layer, a light to heat conversion layer disposed on the base layer, a buffer layer disposed on the light to heat conversion layer, an organic transfer layer disposed on the buffer layer, and a tightening member disposed on a peripheral portion of the organic transfer layer. The tightening member may include an adhesive film having an adhesion strength controlled by an irradiation of an ultraviolet ray. Process failures for manufacturing an organic light emitting display device may be prevented by the donor substrate, so that the organic light emitting display device may ensure improved performances.

Abstract: An integrated circuit includes a circuit and a guard ring. The circuit is over a substrate. The guard ring surrounds the circuit and includes a staggered line. The staggered line comprises a first zigzag line and a second zigzag line. The first zigzag line comprises interconnections formed in at least two GDS layers. The second zigzag line comprises interconnections formed in at least two GDS layers. The first zigzag line and the second zigzag line form a first quadrangle and a second quadrangle.

Abstract: A semiconductor wafer stack and a method of forming a semiconductor device is disclosed. The method includes providing first and second wafers with top and bottom surfaces. The wafers include edge and non-edge regions, and the first wafer includes devices formed in the non-edge region. A first protection seal may be formed at the edge region of the first wafer. The first and second wafers may further be bonded to form a device stack. The protection seal in the device stack contacts the first and second wafers to form a seal, and protects the devices in subsequent processing.

Abstract: A system and method for precision cutting using multiple laser beams is described. The system and method includes a combination of optical components that split the output of a single laser into multiple beams, with the power, polarization status and spot size of each split beam being individually controllable, while providing a circularly polarized beam at the surface of a work piece to be cut by the laser beam. A system and method for tracking manufacture of individual stents is also provided.

Abstract: A method of manufacturing LED packages includes the steps of: forming a conductive circuit layer on a substrate; screen printing a wall layer on the conductive circuit layer to form a trellis with a plurality of wall units, so that regions of the conductive circuit layer surrounded by the wall units are exposed; mounting and electrically connecting at least one LED die on the conductive circuit layer within each of the wall units; molding a transparent layer to cover the LED dies; and cutting along the wall units to form a plurality of LED packages.

Abstract: A semiconductor device has a first interconnect structure formed over the carrier. A semiconductor die is disposed over the first interconnect structure after testing the first interconnect structure to be known good. The semiconductor die in a known good die. A vertical interconnect structure, such as a bump or stud bump, is formed over the first interconnect structure. A discrete semiconductor device is disposed over the first interconnect structure or the second interconnect structure. An encapsulant is deposited over the semiconductor die, first interconnect structure, and vertical interconnect structure. A portion of the encapsulant is removed to expose the vertical interconnect structure. A second interconnect structure is formed over the encapsulant and electrically connected to the vertical interconnect structure. The first interconnect structure or the second interconnect structure includes an insulating layer with an embedded glass cloth, glass cross, filler, or fiber.

Abstract: A semiconductor device including a first conductor layer, a second conductor layer formed over the first conductor layer, a third conductor layer formed over the second conductor layer, a gate trench which passes through the third conductor layer and is formed in the second conductor layer, a first insulating film formed on an inner wall of the gate trench, a second insulating film formed on the inner wall of the gate trench, a first buried conductor layer formed in the gate trench, a gate electrode formed in the gate trench, a fourth conductor layer of the second conductivity type formed on a lower end of the first buried conductor layer and a lower end of the gate trench, and a fifth conduction layer of the first conductivity type formed over the third conductor layer. The first insulating film is thicker than the second insulating film.

Abstract: Methods for forming a semiconductor devices are provided. A plasma pre-treatment operation is performed on a photoresist pattern formed over a material disposed over a substrate, and reduces critical dimensions (CDs) of features of the photoresist pattern to a greater extent at a central portion of the substrate than at outer portions of the substrate, thereby forming a treated pattern with a gradient of CDs. The material is then etched using the treated pattern as a photomask. An overetch operation that tends to reduce CDs of the etched features of the material to a greater extent at outer portions of the substrate than at the central portion of the substrate, is employed. The plasma pre-treatment operation is designed in conjunction with the overetch characteristics and, in combination, the operations produce etched features having CDs with a high degree of uniformity across the substrate.

Abstract: A method of forming a stable nickel silicide layer is provided. The method may include forming a nickel silicide layer on a substrate. A fluorine-rich nickel layer is formed over the nickel silicide layer. The fluorine-rich nickel layer is subjected to a process that drives the fluorine in the fluorine-rich nickel layer into the nickel silicide layer thereunder.

Abstract: Disclosed are non-planar capacitors with finely tuned capacitances and methods of forming them. The capacitors each incorporate one or more semiconductor bodies and one or more gate stacks traversing the one or more semiconductor bodies. At least one first semiconductor body is etched so that it is shorter in length than the others, which are incorporated into other non-planar devices and/or into the same non-planar capacitor. Additionally, at least one gate stack can be formed so that it traverses a first portion and, particularly, an end portion of the shortened semiconductor body and further so that it extends laterally some distance beyond that first portion. In such capacitors, the length of the first portion of the shorted semiconductor body, which corresponds to a capacitor conductor and which is traversed by the gate stack, which corresponds to a capacitor dielectric and another capacitor conductor, is predetermined to achieve a desired capacitance.

Abstract: In various embodiments, photovoltaic devices incorporate discontinuous passivation layers (i) disposed between a thin-film absorber layer and a partner layer, (ii) disposed between the partner layer and a front contact layer, and/or (iii) disposed between a back contact layer and the thin-film absorber layer.

Abstract: A solid state imaging device includes a substrate, in which the substrate includes a photoelectric conversion unit that generates a charge according to a light amount of incident light by a pixel unit, an accumulation unit that divides the charge of the pixel unit which is generated in the photoelectric conversion unit and accumulates the charge, a first element isolation unit that is formed at a boundary of the photoelectric conversion unit of the pixel unit, and a second element isolation unit that is formed at a boundary of the accumulation unit of a divided unit of the pixel.

Abstract: Embodiments include methods of depositing and controlling the deposition of a film in multiple stages. The disclosed deposition and deposition control methods include the optical monitoring of a deposition matrix to determine a time when at least one transition point occurs. In certain embodiments, the transition point or transition points are a stoichiometry point. Methods may also include controlling the length of time in which material is deposited during a deposition stage or controlling the amount of the first, second or subsequent materials deposited during any deposition stage in response to a determination of the time when a selected transition point occurs.

Abstract: There is provided a method for manufacturing a semiconductor device, including forming a film on a substrate by performing a cycle one or more times. The cycle includes forming a first layer containing silicon, nitrogen, and carbon by supplying a first silane-based source having a halogen-based ligand to the substrate and supplying a second silane-based source having amino groups to the substrate. The cycle also includes forming a second layer by modifying the first layer by performing supplying a reactive gas different from each of the sources, to the substrate.

Abstract: A semiconductor buffer structure includes a silicon substrate, a nucleation layer formed on the silicon substrate, and a buffer layer formed on the nucleation layer. The buffer layer includes a first layer formed of a nitride semiconductor material having a uniform composition rate, a second layer formed of the same material as the nucleation layer on the first layer, and a third layer formed of the same material with the same composition ratio as the first layer on the second layer.

Abstract: An integrated circuit may be formed by forming a buried isolation layer in an isolation recess in a single-crystal silicon-based substrate. Exposed lateral surfaces of the substrate at the buried isolation layer are covered with a dielectric sidewall. A seed trench is formed through the buried isolation layer to expose the substrate. A single-crystal silicon-based seed layer is formed through the seed trench, extending above the top surface of the buried isolation layer. A silicon-based non-crystalline layer is formed contacting the seed layer. A cap layer is formed over the non-crystalline layer. A radiant-induced recrystallization process converts the non-crystalline layer to a single-crystal layer aligned with the seed layer. The cap layer is removed and the single-crystal layer is planarized, leaving an isolated semiconductor layer over the buried isolation layer.

Abstract: One illustrative method disclosed herein includes, among other things, forming a fin protection layer around a fin, forming a sacrificial gate electrode above a section of the fin protection layer, forming at least one sidewall spacer adjacent the sacrificial gate electrode, removing the sacrificial gate electrode to define a gate cavity that exposes a portion of the fin protection layer, oxidizing at least the exposed portion of the fin protection layer to thereby form an oxidized portion of the fin protection layer, and removing the oxidized portion of the fin protection layer so as to thereby expose a surface of the fin within the gate cavity.

Abstract: Techniques herein include methods to increase etching selectivity among materials. Techniques herein include a cyclical process of etching and oxidation of a silicon nitride (SiN) spacer and silicon (such as polycrystalline silicon). This technique can increase selectivity to the silicon so that silicon is less likely to be etched or damaged while silicon nitride is etched from sidewalls. Techniques and chemistries as disclosed herein can be more selective to silicon oxide and silicon as compared to silicon nitride. An oxidizing step creates an oxide protection film on silicon surfaces that is comparatively thicker to any oxide film formed on nitride surfaces. As such, techniques here enable better removal of silicon nitride and silicon nitride spacer materials.

Abstract: A method of manufacturing a semiconductor light emitting device includes forming a light emitting structure layer including an active layer on a first substrate. A second substrate is bonded to the light emitting structure layer at a first temperature higher than room temperature. The first substrate is removed from the light emitting structure layer at a second temperature higher than room temperature. The second substrate and the light emitting structure are cooled to reach room temperature. A coefficient of thermal expansion of the second substrate is different from a coefficient of thermal expansion of the active layer.

Abstract: An integrated circuit is formed by forming an isolation mesa over a single crystal substrate which includes silicon, and forming a first epitaxial layer on the substrate by a selective epitaxial process so that a top surface of the first epitaxial layer is coplanar with the top surface of the isolation mesa. A non-selective epitaxial process forms single-crystalline silicon-based semiconductor material on the first epitaxial layer and non-crystalline silicon-based material on the isolation mesa. A cap layer is formed over the second epitaxial layer, and a radiantly-induced recrystallization process causes the non-crystalline silicon-based material to form single-crystalline semiconductor over the isolation mesa.