Abstract: A memory cell container of a DRAM semiconductor memory device and method for manufacturing the cell container are disclosed. The cell includes a container formed in a structural layer such as borophosphosilicate glass. The container is then lined with a polysilicon such as hemispherical grained polysilicon. A dielectric layer is deposited over the polysilicon layer. A barrier layer is deposited over the dielectric layer such that the opening of the container is covered but not the sidewalls or the bottom of the container. The cell is then oxidized and the barrier layer provides protection as an oxygen barrier during the oxidation or any following re-oxidation process.

Abstract: Methods of forming field effect transistors and resultant field effect transistor circuitry are described. In one embodiment, a semiconductive substrate includes a field effect transistor having a body. A first resistive element is received by the substrate and connected between the transistor's gate and the body. A second resistive element is received by the substrate and connected between the body and a reference voltage node. The first and second resistive elements form a voltage divider which is configured to selectively change threshold voltages of the field effect transistor with state changes in the gate voltage. In a preferred embodiment, first and second diode assemblies are positioned over the substrate and connected between the gate and body, and the body and a reference voltage node to provide the voltage divider.

Abstract: A CMOS-compatible FET has a reduced electron affinity polycrystalline or microcrystalline SiC gate that is electrically isolated (floating) or interconnected. The SiC material composition is selected to establish the barrier energy between the SiC gate and a gate insulator. In a memory application, such as a flash EEPROM, the SiC composition is selected to establish a lower barrier energy to reduce write and erase voltages and times or accommodate the particular data charge retention time needed for the particular application. In a light detector or imaging application, the SiC composition is selected to provide sensitivity to the desired wavelength of light. Unlike conventional photodetectors, light is absorbed in the floating gate, thereby ejecting previously stored electrons therefrom. Also unlike conventional photodetectors, the light detector according to the present invention is actually more sensitive to lower energy photons as the semiconductor bandgap is increased.

Abstract: A cluster tool and a number of different processes for making a cobalt-silicide material are disclosed. Combinations of alloyed layers of Co—Ti— along with layers of Co— are arranged and heat treated so as to effectuate a silicide reaction. The resulting structures have extremely low resistance, and show little line width dependence, thus making them particularly attractive for use in semiconductor processing. A cluster tool is configured with appropriate sputter targets/heat assemblies to implement many of the needed operations for the silicide reactions, thus resulting in higher savings, productivity, etc.

Abstract: A semiconductor device having gate oxide with a first thickness and a second thickness is formed by initially implanting a portion of the gate area of the semiconductor substrate with nitrogen ions and then forming a gate oxide on the gate area. Preferably the gate oxide is grown by exposing the gate area to an environment of oxygen. A nitrogen implant inhibits the rate of SiO2 growth in an oxygen environment. Therefore, the portion of the gate area with implanted nitrogen atoms will grow or form a layer of gate oxide, such as SiO2, which is thinner than the portion of the gate area less heavily implanted or not implanted with nitrogen atoms. The gate oxide layer could be deposited rather than growing the gate oxide layer. After forming the gate oxide layer, polysilicon is deposited onto the gate oxide. The semiconductor substrate can then be implanted to form doped drain and source regions. Spacers can then be placed over the drain and source regions and adjacent the ends of the sidewalls of the gate.

Abstract: A method for forming a dual damascene line structure includes forming an inter-metal dielectric including a first region and a second region on a semiconductor substrate, forming a first hard mask material layer on an entire surface of the inter-metal dielectric, removing the first hard mask material layer on the first region, forming a second hard mask material layer on an entire surface of the inter-metal dielectric, forming a hard mask to remove a portion of the first hard mask material layer on the second region, etching the inter-metal dielectric of the first region to a first thickness using the hard mask, exposing the inter-metal dielectric of the second region, and etching the exposed inter-metal dielectric to simultaneously form a via hole and a trench having the via hole.

Abstract: A process for making abrupt, e.g. <20 nm/decade, PN junctions and haloes in, e.g., CMOSFETs having gate lengths of, e.g. <50 nm, uses a mask, e.g., sidewall spacers, during ion implantation of gate, source, and drain regions. The mask is removed after source-drain activation by annealing and source and drain extension regions are then implanted. Then the extension regions are activated. Thereafter halo regions are implanted and activated preferably using spike annealing to prevent their diffusion. The process can also be used to make diodes, bipolar transistors, etc. The activation annealing steps can be combined into a single step near the end of the process.

Abstract: There is provided a method for forming a vertical gate on a vertical array semiconductor device having support devices. The method includes the step of forming a pedestal of the vertical gate from SiGe. The pedestal is etched in a gate conductor (GC) post etch treatment (PET) that is selective with respect to the support devices. A trench top nitride spacer process is performed to obtain a GC SiN spacer combined with a DT (deep trench) top SiN spacer, wherein the GC SiN spacer and the DT top SiN spacer isolate a bitline contact from the vertical gate with respect to critical dimension and overlay.

Abstract: The invention encompasses a method of forming an opening in a substrate. A first expanse of a first material is formed over the substrate, and such expanse comprises a sidewall edge. A second material is formed along the sidewall edge, and subsequently a second expanse of the first material is formed over the substrate and separated from the first expanse by the second material. The first and second expanses together define a mask. The second material is removed with an etch selective for the second material relative to the first material to form an opening extending through the mask. The substrate is etched through the opening in the mask to extend the opening into the substrate. In a particular embodiment of the invention, the opening is filled with insulative material to form a trenched isolation region. In another embodiment of the invention, the opening is filled with a conductive material to form a transistor gate.

Abstract: A method for fabricating a trench capacitor for a semiconductor memory includes forming a masking layer in a trench that is disposed in a substrate. Nanocrystallites, which are used to pattern the masking layer, are deposited on the masking layer. Microtrenches are etched into the substrate in a lower region of the trench by the patterned masking layer. The microtrenches form a roughened trench sidewall. As a result, the outer capacitor electrode is formed with a larger surface area, allowing the trench capacitor to have a higher capacitance.

Abstract: A new method of reducing copper hillocks in copper metallization is described. An opening is made through a dielectric layer overlying a substrate on a wafer. A copper layer is formed overlying the dielectric layer and completely filling the opening. The copper layer is polished back to leave the copper layer only within the opening. Copper hillocks are reduced by: coating an oxide layer over the copper layer and the dielectric layer, thereafter heating the wafer using NH3 plasma, and thereafter depositing a capping layer overlying the oxide layer wherein the time lapse between polishing back the copper layer and depositing the capping layer is less than one day (24 hours).

Abstract: This invention provides a novel application of a semiconductor light emitting element or light emitting chip preferably disposed on the underside surface of a clear or translucent substrate. In addition connecting wires leading from said element to the perimeter of the substrate connecting to contact pads leading to a circuit board. The conductors are deposited on the substrate using thin film technology. Preferably the light emitting element is packaged in a flip chip having connecting bumps only on one side.

Abstract: A complementary metal oxide semiconductor (CMOS) device having silicide contacts that are self-aligned to deep junction edges formed within a surface of a semiconductor substrate as well as a method of manufacturing the same are disclosed. Specifically, the CMOS device includes a plurality of patterned gate stack regions formed on a surface of a semiconductor substrate. Each plurality of patterned gate stack regions includes an L-shaped nitride spacer formed on exposed vertical sidewalls thereof, the L-shaped nitride spacer having a vertical element and a horizontal element, wherein the horizontal element is formed on a portion of the substrate that abuts each patterned gate stack region. Silicide contacts are located on other portions of the semiconductor substrate between adjacent patterned gate stack regions not containing the horizontal element of the L-shaped nitride spacer.

Abstract: The present invention relates to a method for crystallizing the active layer of a thin film transistor utilizing crystal filtering technique. According to the conventional metal induced lateral crystallization (MILC) method, amorphous silicon layer can be crystallized into poly-crystal silicon layer. According the crystal filtering technique of the present invention, amorphous silicon layer can be single-crystallized by filtering a single crystal component from the poly-crystal region being crystallized by MILC. The TFT fabricated including an active layer crystallized according to the present method has significantly improved electrical characteristics such as electron mobility and leakage current as compared to the TFT including a poly-crystal silicon active layer made by conventional methods. The invention also provides various TFT fabrication methods applying the crystal filtering technique.

Abstract: A manufacturing method for a semiconductor storage device with a floating gate includes a first step for depositing a first thermally-oxidized film (14) on a poly-silicon film (12) that has been etched to a desired depth so as to have a tapered etched end by using a silicon nitride film (13) having an opening as a mask, a step for depositing a first NSG film side wall spacer (115) that covers the tapered portion on an opening side wall of the silicon nitride film (13) and adding heat treatment thereto, a step for forming a second NSG film side wall spacer (15) on the inner side of the first NSG film side wall spacer 115, a step for forming a poly-silicon plug (18), then depositing a second thermally-oxidized film (19) on the poly-silicon plug (18), a step for removing the silicon nitride film (13), then etching the poly-silicon film (12), and a step for removing the first NSG film side wall spacer (115).

Abstract: A chip-on-chip module and associated method of formation. First and second semiconductor chips are coupled together. The first chip comprises a first wiring layer and a first electrically conductive substrate on first and second sides, respectively, of the first chip. A supply voltage VDD is adapted to be electrically coupled to the second side of the first chip. The second chip comprises a second wiring layer and a second electrically conductive substrate on first and second sides, respectively, of the second chip. A ground voltage GND is adapted to be electrically coupled to the second side of the second chip. The first side of the first chip is electrically coupled to the first side of the second chip. The supply voltage VDD and the ground voltage GND are adapted to provide power to the first and second chips.

Abstract: A method for manufacturing a semiconductor device having an n-type MIS transistor and a p-type MIS transistor comprises forming a first gate insulating film in a first area where the n-type MIS transistor is to be formed, depositing a first conductive film on the first gate insulating film in the first area, the first conductive film containing silicon, a metal element selected from tungsten and molybdenum and an impurity element selected from phosphorus and arsenic, forming a second gate insulating film in a second area where the p-type MIS transistor is to be formed, and forming a second conductive film on the second gate insulating film in the second area, the second conductive film having a work function higher than that of the first conductive film.

Abstract: The vertical bipolar transistor includes an SiGe heterojunction base formed by a stack of layers of silicon and silicon-germanium resting on an initial layer of silicon nitride extending over a side insulation region surrounding the upper part of the intrinsic collector. The stack of layers also extends on the surface of the intrinsic collector which lies inside a window formed in the initial layer of silicon nitride.

Abstract: A flip chip assembly process forming an underfill encapsulant. The method includes providing a chip having an active surface and a plurality of conductive bumps arranged in array with a predetermined bump pitch thereon, providing a substrate having a surface, having a die-attaching region, having a plurality of pads with previously formed solder paste thereon, arranged in array with a predetermined pad pitch the same as the active surface, forming an encapsulant in the die-attaching region excluding the pads, using a stencil and screen printing, and attaching the chip onto the substrate resulted from one-to-one joining the conductive bumps and the pads. A tool forming an underfill encapsulant is includes a stencil having at least one printing region, including a plurality of openings, a plurality of covers arranged in array with a predetermined cover pitch, and a plurality of connecting devices, connecting every two neighboring covers, or each cover with other regions of the stencil.

Abstract: A method for forming one or more FinFET devices includes forming a source region and a drain region in an oxide layer, where the oxide layer is disposed on a substrate, and etching the oxide layer between the source region and the drain region to form a group of oxide walls and channels for a first device. The method further includes depositing a connector material over the oxide walls and channels for the first device, forming a gate mask for the first device, removing the connector material from the channels, depositing channel material in the channels for the first device, forming a gate dielectric for first device over the channels, depositing a gate material over the gate dielectric for the first device, and patterning and etching the gate material to form at least one gate electrode for the first device.