Abstract: A wiring pattern has been enlarged by mutually different values, thereby forming two enlarged wiring patterns are formed. Then, regions where the two enlarged wiring patterns overlap each other are removed, thereby forming a dummy pattern. Alternatively, a simple-figure pattern made of simple figures is formed and a dummy pattern is formed using the simple-figure pattern. A gap that is not wider than a predetermined value is located in a final wiring pattern made of the wiring pattern and the dummy pattern is defined as an air gap region. Thus, an interconnection structure incorporating air gaps between wiring patterns is formed.

Abstract: In a method for manufacturing a semiconductor device, an N type single-crystal silicon substrate having a first silicon oxide film and a P type poly-crystal silicon layer is provided. A silicon nitride film is formed on the P type poly-crystal silicon layer. A side wall of the silicon nitride film is formed in an opening in the P type poly-crystal silicon layer above a portion expected to provide an active region. The first silicon oxide film has an opening therein which is larger than the opening formed in the P type poly-crystal silicon layer. Then, an N type IV-group semiconductor mixed crystal layer having a smaller band gap than silicon to a desired thickness is grown on the single-crystal silicon substrate on which a surface of the portion expected to provide said active region is exposed. A non-doped single-crystal silicon layer is grown on the IV-group semiconductor mixed crystal layer to a desired thickness.

Abstract: A semiconductor device and a process for fabricating the device, the process including steps of depositing on the silicon substrate a layer comprising at least one high-K dielectric material, whereby a quantity of silicon dioxide is formed at an interface between the silicon substrate and the high-K dielectric material layer; depositing on the high-K dielectric material layer a layer of a metal; and diffusing the metal through the high-K dielectric material layer, whereby the metal reduces at least a portion of the silicon dioxide to silicon and the metal is oxidized to form a dielectric material having a K value greater than silicon dioxide. In another embodiment, the metal is implanted into the interfacial layer. A semiconductor device including such metal layer and implanted metal is also provided.

Abstract: The present invention provides a method for fabricating improved integrated circuit devices. The method of the present invention enables selective hardening of gate oxide layers and includes providing a semiconductor substrate having a gate oxide layer formed thereover. A resist is then formed over the gate oxide layer and patterned to expose one or more areas of the gate oxide layer which are to be hardened. The exposed portions of the gate oxide layer are then hardened using a true remote plasma nitridation (RPN) scheme or a high-density plasma (HDP) RPN scheme. Because the RPN scheme used in the method of the present invention runs at low temperature, the patterned resist remains stable through the RPN process, and those areas of gate oxide layer which are exposed by the patterned resist are selectively hardened by the RPN treatment, while those areas covered by the patterned resist remain unaffected.

Abstract: A method of fabricating a contact-less array of non-volatile memory cells includes: (A) forming over the substrate three stacks S1, S2 and S3 of first and second polysilicon layers; (B) forming in the substrate a drain region between the stacks S1 and S2, self-aligned to the edges of stacks S1 and S2, (C) forming side-wall spacers adjacent to edges of each polysilicon stack, (D) forming in the substrate a source region between stacks S2 and S3, self-aligned to the side-wall spacers; (E) forming a composite layer of HTO-Nitride-Polysilicon (ONP) over the array of memory cells immediately after step (B); (F) converting the ONP composite layer to ONO composite layer after step (D); (G) anisotropically etching the ONO composite layer to form ONO side-wall spacers adjacent to edges of the polysilicon stacks; and (H) growing select gate oxide over the row of polysilicon.

Abstract: The invention relates to a high density read only memory and fabrication method thereof through fabricating a plurality of spaced post transistors on a wafer by implanting and trench etching wherein each post transistor has four vertical surfaces with one of vertical surfaces as a short circuit junction between substrate and source and a read only memory (ROM) cell formed on each of the three remaining vertical surfaces. Therefore, the invention can fabricate three ROM cells in a single post transistor having a high density feature for storing three-bit data.

Abstract: A switch includes a conductive region, a membrane, and a dielectric region. The dielectric region is formed from a dielectric material and is disposed between the membrane and the conductive region. When a sufficient voltage is applied between the conductive region and the membrane, a capacitive coupling between the membrane and the conductive region is effected. The dielectric material has a resistivity sufficiently low to inhibit charge accumulation in the dielectric region during operation of the switch.

Abstract: A method of forming a bump on a substrate such as a semiconductor wafer or flip chip without producing metal ribbon residue. The method includes the step of providing a semiconductor device having a contact pad and having an upper passivation layer and an opening formed in the upper passivation layer exposing a portion of the contact pad. An under bump metallurgy is deposited over the upper passivation layer and the contact pad. A photoresist layer is deposited over the under bump metallurgy. The photoresist layer is a dry film photoresist. The photoresist layer is patterned to provide an opening in the photoresist layers down to the under bump metallurgy and aligned with the contact pad. Additional energy is applied to the photoresist layer to improve the adhesion of the photoresist layer to the under bump metallurgy. An electrically conductive material is deposited into the opening formed in the photoresist layers and overlying the under bump metallurgy and aligned with contact pad.

Abstract: An electrical interconnection method includes: a) providing two conductive layers separated by an insulating material on a semiconductor wafer; b) etching the conductive layers and insulating material to define and outwardly expose a sidewall of each conductive layer; c) depositing an electrically conductive material over the etched conductive layers and their respective sidewalls; and d) anisotropically etching the conductive material to define an electrically conductive sidewall link electrically interconnecting the two conductive layers. Such is utilizable to make thin film transistors and other circuitry.

Abstract: A method of fabricating a ferroelectric capacitor is disclosed. The method comprises the decreases a reduction in a bottom electrode material during formation of the ferroelectric dielectric portion of the capacitor. In the above manner, a fatigue resistance of the ferroelectric capacitor is increased substantially.

Abstract: A method of forming a bottom electrode of a capacitor in a memory device. A plurality of deep trenches is formed, in which the number of first deep trenches within an active area is higher than that of the second deep trenches within a peripheral area. After a doped oxide layer is formed, a photoresist layer is formed on the doped oxide layer to fill the deep trenches. Then, exposure is employed on the photoresist layer with a predetermined incident angle of light source, wherein the photoresist layer outside the level of the deep trenches is exposed, and the photoresist layer inside the deep trenches is not. Thus, the photoresist layer exposed and outside the level of the deep trenches is removed, and the photoresist layer that is not exposed and inside the deep trenches is retained. Next, a part of the photoresist layer inside the deep trenches is removed, as is the doped oxide layer outside the level of the photoresist layer.

Abstract: There is provided a semiconductor device manufacturing method having a ferroelectric or high-dielectric capacitor, which comprises the steps of forming an underlying insulating film over a semiconductor substrate, forming a first conductive film on the underlying insulating film, forming a dielectric film consisting of ferroelectric material and high-dielectric material on the first conductive film, forming a second conductive film on the dielectric film, etching selectively the second conductive film in a first atmosphere containing a bromine to form a capacitor upper electrode, etching selectively the dielectric film in a second atmosphere containing a chlorine to form a capacitor dielectric film, and etching selectively the first conductive film in a third atmosphere containing the bromine to form a capacitor lower electrode.

Abstract: An apparatus for providing mechanical support to a column grid array package is disclosed. The column grid array package uses solder columns to provide electrical connections between a ceramic substrate and a printed circuit board. The ceramic substrate has two sides, with an integrated circuit chip mounted on one side and many input/output pads mounted on the other side. Solder columns are attached between the input/output pads and the printed circuit board. A corner post is located at each corner of the column grid array package to secure the position of the ceramic substrate in relation to the printed circuit board.

Abstract: The present invention relates generally to semiconductor memory devices and more particularly to multi-bit flash electrically erasable programmable read only memory (EEPROM) devices that employ charge trapping within a floating gate to indicate a 0 or 1 bit state. A memory device is provided, according to an aspect of the invention, comprising a floating gate transistor having dual polysilicon floating gates with an isolation opening between floating gates. Processes for making the memory device according to the invention are also disclosed.

Abstract: A semiconductor device fabrication method includes forming a first interconnect and a second interconnect from aluminum or aluminum alloy. The first and second interconnects are formed at different layers and are connected to each other via metal not including aluminum. A hole is provided at the second interconnect, to suppress aluminum loss at ends of the interconnect.

Abstract: In accordance with the present invention, the gate length and the gate insulation film thickness are different between the p-channel MOS field effect transistors serving as the driver gates and the n-channel MOS field effect transistors forming the flip flop. Namely, the p-channel MOS field effect transistors serving as the driver gates have a larger gate length and a smaller gate oxide film thickness than the n-channel MOS field effect transistors forming the flip flop.

Abstract: There is described a semiconductor device having a storage node capacitor structure suitable for rendering memory cells compact, and storage nodes are prevented from tilting. The device includes a storage node which has a vertical surface extending in the direction perpendicular to the surface of a semiconductor substrate, and a dielectric film for tilt prevention purposes which is brought into close contact with the side surface of the vertical surface and which prevents the vertical surface from tilting.

Abstract: Structures, systems and methods are provide for multilevel wiring interconnects in an integrated circuit assembly which alleviate problems associated with integrated circuit size and performance. The structures, systems and methods of the present invention include a method for forming multilevel wiring interconnects in an integrated circuit assembly. The method includes forming a number of multilayer metal lines separated by a number of air gaps above a substrate. A silicide layer is formed on the number of multilayer metal lines. The silicide layer is oxidized. And, a low dielectric constant insulator is deposited to fill a number of interstices created by the number of air gaps between the number of multilayer metal lines. In one embodiment, forming the number of multilayer metal lines includes a first conductor bridge level. In one embodiment, forming a silicide layer on the number of multilayer metal lines includes using a pyrolysis of silane at a temperature of between 300 and 500 degrees Celsius.

Abstract: A method and structure for the electrical characterization of a semiconductor device comprising, first, forming a hole having a diameter less than 0.15 &mgr;m, wherein the hole is created using focused ion beam (FIB) etching, and through at least a protective cap layer formed over the device. The FIB etching occurs in an electron mode using a beam current less than 35 &rgr;A with an aperture size less than 50 &mgr;m, and at an acceleration voltage of about 50 kV. Second, the surface of the hole is coated with a metal, preferably using chemical vapor deposition (CVD) and preferably using a FIB device. Third, a metal pad is deposited, preferably by FIB CVD, over the hole. Fourth, the pad is probed to determine characteristics and/or detect defects of the electrical device. The present invention allows for electrical characterization without causing damage to the device or its features.

Abstract: A method for making an integrated circuit device includes forming source and drain regions in a semiconductor substrate and defining a channel region therebetween, forming a graded, grown, gate oxide layer adjacent the channel region, forming a nitride layer adjacent the gate oxide layer, and forming a gate electrode layer adjacent the nitride layer. The gate oxide layer may be formed by growing a first oxide portion by upwardly ramping the channel region to a first temperature lower than a glass transition temperature, and exposing the channel region to an oxidizing ambient at the first temperature and for a first time period. A second oxide portion may be grown between the first oxide portion and the channel region by exposing the channel region to an oxidizing ambient at a second temperature higher than the glass transition temperature for a second time period so that the second oxide portion has a thickness in a range of about 2% to about 75% of a total thickness of the gate oxide layer.