Abstract: In a method of producing an ohmic contact to a p-type .alpha.-SiC layer in a semiconductor device, layers of aluminum, titanium and silicon are deposited on the .alpha.-SiC layer, and the deposited layers are annealed to convert at least a part of the deposited layers to aluminum-titanium-silicide.

Abstract: An IGFET with metal spacers is disclosed. The IGFET includes a gate electrode on a gate insulator on a semiconductor substrate. Sidewall insulators are adjacent to opposing vertical edges of the gate electrode, and metal spacers are formed on the substrate and adjacent to the sidewall insulators. The metal spacers are electrically isolated from the gate electrode but contact portions of the drain and the source. Preferably, the metal spacers are adjacent to edges of the gate insulator beneath the sidewall insulators. The metal spacers are formed by depositing a metal layer over the substrate then applying an anisotropic etch. In one embodiment, the metal spacers contact lightly and heavily doped drain and source regions, thereby increasing the conductivity between the heavily doped drain and source regions and the channel underlying the gate electrode. The metal spacers can also provide low resistance drain and source contacts.

Abstract: The method for fabrication of a non-symmetrical IGFET of the present invention includes providing a semiconductor substrate having an insulating film and a gate material. A first portion of the gate material overlying a first region of the semiconductor substrate is removed forming a first sidewall of a gate electrode A dopant is implanted into the first region after forming the first sidewall. After the first region is implanted, a second portion of the gate material overlying a second region of the semiconductor substrate is then removed forming a second sidewall of the gate electrode. A dopant is implanted into the second region after forming the second sidewall. Spacers are formed adjacent to each of the sidewalls of the gate electrode. Then, a dopant is then implanted into portions of the first and second regions of the semiconductor substrate outside the gate electrode and the spacers.

Abstract: CMOS transistors are formed by a damascene process resulting in field oxide regions exhibiting essentially no bird's beak portions. A trench isolation is also formed in a source/drain region each transistor between adjacent junctions.

Abstract: A method for preparing an epitaxial silicon wafer in a reactor is provided. The method comprises the steps of depositing an epitaxial layer on a surface of a silicon wafer contained in the reactor at an elevated temperature; purging the reactor with hydrogen after the epitaxial deposition; and cooling the reactor to an appropriate temperature which allows hydrogen passivation of the surface of the epitaxial layer. This prevents the formation of an oxide layer on the surface of the epitaxial layer for a sufficient amount of time to allow an accurate measurement of a carrier density profile of the epitaxial silicon wafer.

Abstract: Semiconductor regions (2, 12) includes pillar-like projections (3, 13) extending vertically from major surfaces of the semiconductor regions and each having a vertical outer surface and an inner surface opposite to the outer surface. Vertical MOS transistors includes gate electrodes (4, 14) opposed to the outer surfaces of the pillar-like projections (3, 13) with gate insulating films (5, 15) interposed therebetween, with their bottom surfaces opposed to the major surfaces of the semiconductor regions (2, 12) with the gate insulating films (5, 15) interposed therebetween, source regions (6, 16) formed in upper end portions of the pillar-like projections (3, 13), drain regions (7, 17) formed in the major surfaces of the semiconductor regions (2, 12) so as to partly overlap bottom surfaces of the gate electrodes (4, 14), and back gate electrodes (8, 18) opposed to the inner surfaces of the pillar-like projections (3, 13) with back gate insulating films (9, 19) interposed therebetween.

Abstract: A process is provided for producing active and passive devices on various levels of a semiconductor topography. As such, the present process can achieve device formation in three dimensions to enhance the overall density at which an integrated circuit is formed. The multi-level fabrication process not only adds to the overall circuit density, but does so with emphasis placed on high performance interconnection between devices on separate levels. The interconnect configuration is made as short as possible between features within one transistor level to features within another transistor level. This interconnect scheme lowers resistivity by forming a gate conductor of an upper level transistor upon a gate conductor of lower level transistor. Alternatively, the gate conductors can be a single conductive entity. In order to abut the gate conductors together, or form a single gate conductor, the upper level transistor is inverted relative to the lower level transistor.

Abstract: Disclosed is a method of forming electrodes on diamond comprising the steps of: forming a mask pattern on diamond or diamond film; performing a treatment of the diamond surface by a plasma of inert gases; forming an electrode film on the whole surface of the specimen; and removing the mask, thereby forming a specified pattern of the electrodes. By this method, it is possible to form electrodes having high adhesion to diamond and diamond film for electronic devices.

Abstract: A method for fabricating a transistor includes the steps of forming a gate insulation film on a substrate, forming a gate electrode on the gate insulation film and forming a first insulation film pattern on the gate electrode. A side wall spacer is formed at side surfaces of the first insulation film pattern and the gate electrode. The gate insulation film is etched to expose a portion of a surface of the substrate. An epitaxial layer is formed on the substrate where the gate insulation film is etched. The side wall spacer is removed and a thermal oxide film is grown on a portion corresponding to where the side wall spacer is removed and on an upper portion of the epitaxial layer. A source/drain region is formed by ion-implanting an impurity into the epitaxial layer.

Abstract: A semiconductor memory device is provided which includes: a memory cell portion including at least one gate electrode formed on a semiconductor substrate and a plurality of source/drain regions formed in the semiconductor substrate and extending parallel to each other and perpendicular to the gate electrode, the gate electrode and the plurality of source/drain regions constituting a plurality of first conductivity type channel transistors; and a peripheral circuitry portion including a first conductivity type channel transistor having a gate electrode formed on the semiconductor substrate and source/drain regions; wherein channels of the first conductivity type channel transistors in the memory cell portion each have a higher impurity concentration than a channel of the first conductivity type channel transistor in the peripheral circuitry portion.

Abstract: A method for fabricating alignment marks in a twin-well integrated circuit without using a zero-layer photomask is disclosed.

Abstract: The preferred embodiment of the present invention overcomes the limitations of the prior art and provides a device and method to increase the latch-up immunity of CMOS devices by forming implants at the well edges. The preferred method uses hybrid resist to form these implants at the edges of the N-wells and/or P-wells. The implants reduce the lifetime of minority carriers in the parasitic transistor, and hence reduce the gain of the parasitic transistor. This reduces the propensity of the CMOS device to latch-up. The preferred embodiment method allows these implants to be formed without requiring additional masking steps over prior art methods. Furthermore, the preferred method for forming the implants results in implants that are self aligned to the edges of the wells.

Abstract: Corner conduction in a conduction channel of a field effect transistor is controlled by the geometrical configuration of the gate oxide and gate electrode at the sides of the conduction channel. Rounding the corners of the conduction channel or forming depressions at edges of trench structures such as deep or shallow trench isolation structures and/or trench capacitors develop recesses in a surface of a substrate at an interface of active areas and trench structures in which a portion of the gate oxide and gate electrode are formed so that the gate oxide and gate electrode effectively wrap around a portion of the conduction channel of the transistor. Particularly when such transistors are formed in accordance with sub-micron design rules, the geometry of the gate electrode allows the electric field in the conduction channel to be modified without angled implantation to regulate the effects of corner conduction in the conduction channel.

Abstract: Methods of manufacturing trench-bounded buried-channel p-type metal oxide semiconductor field effect transistors (p-MOSFETs), as used in dynamic random access memory (DRAM) technologies, for significantly reducing the anomalous buried-channel p-MOSFET sensitivity to device width. In one embodiment, the method comprises the initiation of a low temperature annealing step using an inert gas after the deep phosphorous n-well implant step, and prior to the boron buried-channel implant and 850.degree. C. gate oxidation steps. Alternatively, the annealing step may be performed after the boron buried-channel implant and prior to the 850.degree. C. gate oxidation step. In another embodiment, a rapid thermal oxidation (RTO) step is substituted for the 850.degree. C. gate oxidation step, following the deep phosphorous n-well and boron buried-channel implant steps. Alternatively, an 850.degree. C. gate oxidation step may follow the RTO gate oxidation step.

Abstract: A titanium film and a titanium nitride film are sequentially formed on a polysilicon plug. Next, the titanium nitride film is oxidized to form an oxidized titanium nitride film. Thereafter, a lower electrode and a PZT film are formed. A diffusion barrier layer is prepared from the oxidized titanium nitride film and is oxidized before the lower electrode is formed. As a result, unlike in prior art, the diffusion barrier layer is not oxidized after the lower electrode is formed. Peel-off between the diffusion barrier layer and the lower electrode due to the oxidation is thus prevented.

Abstract: A method for fabricating a T-shaped gate electrode includes the steps of: forming a fine gate pattern on a semiconductor substrate; forming an insulating layer on the semiconductor substrate on which the gate pattern is formed, and forming a planarizing layer on the insulating layer to planarize the surface of the semiconductor substrate; etching the planarizing layer to expose the top of the insulating layer; isotropically etching the insulating layer to expose the gate pattern using the planarizing layer as a mask; etching the exposed gate pattern to selectively expose the semiconductor substrate; depositing a gate metal to cover the exposed substrate, the insulating layer and the planarizing layer, to form a T-shaped gate; and simultaneously removing the planarizing layer, thereby forming a T-shaped gate metal with improved productivity.

Abstract: A semiconductor substrate for GaP type light emitting devices which includes an n-type single crystal substrate, an n-type GaP layer, and a p-type GaP layer formed on the n-type GaP single crystal substrate. The carbon concentration in the n-type GaP single crystal substrate is more than 1.0.times.10.sup.16 atoms/cc but less than 1.0.times.10.sup.17 atoms/cc. The n-type GaP single crystal substrate is obtained from an n-type GaP single crystal grown by the Liquid Encapsulation Czochralski method wherein B.sub.2 O.sub.3 containing water corresponding to 200 ppm or more is used as an encapsulation liquid.

Abstract: In one aspect of the invention, a semiconductor processing method includes: a) providing a semiconductor substrate; b) defining a first conductivity type region and a second conductivity type region of the semiconductor substrate; c) providing a first transistor gate over the first type region which defines a first source area and a first drain area operatively adjacent thereto; d) providing a second transistor gate over the second type region which defines a second source area and a second drain area operatively adjacent thereto; and e) blanket implanting a conductivity enhancing dopant of the second conductivity type through the first source and drain areas of the first conductivity region and the second source and drain areas of the second conductivity region to provide second conductivity type regular LDD implant regions within the substrate operatively adjacent the first transistor gate and to provide second conductivity type halo implant regions within the substrate operatively adjacent the second trans

Abstract: An LC element, semiconductor device and a manufacturing method thereof whereby a channel 22 is formed by applying a voltage to a gate electrode 10 having a predetermined shape formed on a p-Si substrate 30 via an insulation layer 26, whereby a connection is formed between a first diffusion region 12 and a second diffusion region 14 formed at separated positions near the surface of the p-Si substrate 30; both the channel 22 gate electrode 10 function as inductors, and between these a distributed constant type capacitor is formed, and possessing excellent attenuation characteristics over a wide band. This LC element and semiconductor device can be easily manufactured by using MOS manufacturing technology; in the case of manufacturing as a portion of a semiconductor substrate, component assembly work in subsequent processing can be omitted. Also these can be formed as a portion of an IC or LSI device.

Abstract: In a method for making an electrical connection between a trench storage capacitor and an access transistor in a DRAM cell, the electrical connection is formed through the selectively controlled outdiffusion of either N-type or P-type dopants present in the trench through a single crystalline semiconducting material which is grown by epitaxy (epi) from the trench sidewall. This epitaxially grown single crystalline layer acts as a barrier to excessive dopant outdiffusion which can occur in the processing of conventional DRAMs.