Abstract: A compact RC semiconductor structure suitable for integrated RC and RCD networks contains a semiconductor body (10), an overlying dielectric layer (14), and a resistive plate (16A) situated over the dielectric layer. The resistive plate constitutes both a resistor and at least part of the upper plate of a capacitor whose lower plate (12) is formed with part of the semiconductor body below the dielectric layer. A capacitive structure which provides high ESD protection is formed with a semiconductor body (10) that contains a heavily doped surface layer (12) whose sheet resistance is no more than 5 ohms/square. The surface layer constitutes the lower plate for a capacitor whose upper plate is formed with a conductive plate (16A) situated on a dielectric layer (14) overlying the semiconductor body.

Abstract: A method for integrating one or more microelectromechanical (MEM) devices with electronic circuitry. The method comprises the steps of forming each MEM device within a cavity below a device surface of the substrate; encapsulating the MEM device prior to forming electronic circuitry on the substrate; and releasing the MEM device for operation after fabrication of the electronic circuitry. Planarization of the encapsulated MEM device prior to formation of the electronic circuitry allows the use of standard processing steps for fabrication of the electronic circuitry.

Abstract: A trench is formed on a main surface of a p+ type monocrystalline silicon substrate. A silicon oxide film is formed extending from the inner surface of trench onto the main surface of p+ type monocrystalline silicon substrate. The thickness of a corner portion positioned on the upper end corner portion of the sidewall of trench in silicon oxide film is larger than the thickness of silicon oxide film positioned on the sidewall of trench. An n type polycrystalline silicon layer extending from the inside of trench onto the main surface of p+ type monocrystalline silicon substrate is formed on silicon oxide film. Thus, a semiconductor device having a trench structure with an improved breakdown voltage for an insulating layer positioned on an upper end corner portion of the sidewall of a trench is obtained.

Abstract: A CMOS integrated circuit with field isolation including an NFET(s) having an isolated P-well, wherein the isolated P-well is adjusted so that it does not extend below the field isolation (e.g., STI) and the width and doping of the P-well and an underlying buried N-well is adjusted so that the depletion regions of the source/drain (S-D) diode and also the well-diode just meet (merge) without overlap in the P-well. The semiconductor device obtains bipolar effect and reduced junction capacitance in a bulk single-crystal technology. A method for fabricating the semiconductor device is also provided.

Abstract: A method of forming MOS components provides that after the formation of the gate and the doped source/drain regions, a polysilicon layer is deposited and planarized using a chemical-mechanical polishing method. The resulting unremoved polysilicon layer acts as source/drain terminals. Through these arrangements, the ion doped source/drain regions will have shallow junctions, yet their junction integrity will not be compromised by subsequent contact window etching and metallization processes. Furthermore, the front-end processes for forming the MOS component provide a good planar surface that offers great convenience for the performance of subsequent back-end processes.

Abstract: In a thin film transistor (TFT) having an active layer formed on an insulating film, a gate electrode is formed by using a metal material such as aluminum, an gate insulating film is formed by using a silicon insulator such as silicon oxide or silicon nitride. A film is formed on the gate electrode and the gate insulting film by using a silicon material such as amorphous silicon and then etched with anisotropic etching to form side walls made of a silicon material in sides of the gate electrode. In this etching, since an etching rate of the side walls is larger than that of the gate insulating film, the gate insulating film is not almost etched.

Abstract: A novel, reliable, high performance MOS transistor with a composite gate electrode which is compatible with standard CMOS fabrication processes. The composite gate electrode comprises a polysilicon layer formed on a highly conductive layer. The composite gate electrode is formed on a gate insulating layer which is formed on a silicon substrate. A pair of source/drain regions are formed in the substrate and are self-aligned to the outside edges of the composite gate electrode.

Abstract: A method of forming a T-type gate electrode of a high-frequency transistor having excellent high-frequency power transfer characteristic with no concave portions and protrusions. A first resist pattern having a first relatively narrow opening is formed on a semiconductor substrate and a leg portion of the electrode is formed in the first opening by depositing electrode metal on the substrate. A second resist pattern having a second relatively wide opening is formed over the electrode leg portion for locating an exposed tip of the electrode leg portion in the bottom of the second opening and forming a head portion of the electrode by depositing electrode metal in the second opening. The head portion is etched for removing any protrusions formed on the head portion.

Abstract: Method for manufacturing a metal semiconductor field-effect transistor (MESFET) in which a gate area contacting a semiconductor surface is diminished and a gate cross area is increased, to improve frequency characteristics of a device is disclosed, including the steps of: forming an n-type GaAs layer and a heavily doped n.sup.+ -type GaAs layer on a substrate, sequentially; forming a first insulating layer on the heavily doped n.sup.

Abstract: Novel memory cells utilize source-side injection, allowing very small programming currents. If desired, to-be-programmed cells are programmed simultaneously while not requiring an unacceptably large programming current for any given programming operation. In one embodiment, memory arrays are organized in sectors with each sector being formed of a single column or a group of columns having their control gates connected in common. In one embodiment, a high speed shift register is used in place of a row decoder to serially shift in data for the word lines, with all data for each word line of a sector being contained in the shift register on completion of its serial loading. In one embodiment, speed is improved by utilizing a parallel loaded buffer register which receives parallel data from the high speed shift register and holds that data during the write operation, allowing the shift register to receive serial loaded data during the write operation for use in a subsequent write operation.

Abstract: Method for manufacturing a self-aligned T-type gate in which an ohmic electrode and a T-type gate electrode are simultaneously disposed and its excellent reproductivity is obtained and the overall process is simplified is disclosed, including the steps of: forming an insulating layer, a first metal layer, and a first photoresist layer and patterning the first photoresist layer; selectively removing the first metal layer such that the first metal layer under a pattern of the first photoresist layer is under-cut in a mesa form to form a gate pattern, and selectively removing the insulating layer such that the insulating layer under the first metal layer is under-cut in a same form as the first metal layer so as to pattern ohmic electrode regions; forming a second metal layer on the ohmic electrode regions to form ohmic electrodes and selectively removing the insulating layer to be unsymmetrical with respect to the center of the first metal layer; forming a second photoresist layer on the entire surface inclusiv

Abstract: The present invention concerns single-gate and double-gate field effect transistors having a sidewall source contact and a sidewall drain contact, and methods for making such field effect transistors. The channel of the present field effect transistors is raised with respect to the support structure underneath and the source and drain regions form an integral part of the channel.

Abstract: A method of fabricating a short-channel MOS device on a substrate is provided. First, stacked pad oxide/nitride layers are formed on the substrate. Then a patterned photoresist film is formed on the planned gate region which covers the gate region and its sidewall spacers. A LPD (Liquid Phase Deposition) oxide is selectively deposited on the pad nitride layer by a liquid phase deposition process, except on the pre-formed photoresist film. After removing the photoresist layer nitride spacers leaning against the LPD oxide layer are formed by lithography and etching. The width of the nitride spacers controls the channel length of the MOS device. After forming a gate structure laterally sandwiched by the nitride spacers on the exposed substrate, a two-stage salicide process, which can form shallow junctions and self-aligned contacts on the source and the drain, is performed to complete the MOS device.

Abstract: The present invention relates to a method of forming lightly doped drains in metallic oxide semiconductor (MOS) components. The method includes forming a first, second, and third insulating layer above a silicon substrate having a gate, etching back the layers to leave behind L-shaped first spacers on sidewalls of the gate, followed by doping second type ions into the silicon substrate to form first lightly doped drains in the silicon substrate surface below the L-shaped first spacers, and second lightly doped drains in the silicon substrate surface elsewhere, further forming a fourth insulating to form third spacers, and using the using the third spacers, the first insulating layer, and the gate as masks when doping second type ions into the silicon substrate so as to form source/drain regions in silicon substrate surfaces not covered by the third spacers. Such a method produces greater yield and reduces leakage current from the transistor components.

Abstract: Disclosed is a method of forming electrodes on diamond comprising the steps of: forming a mask pattern on diamond or diamond film; performing a treatment of the diamond surface by a plasma of inert gases; forming an electrode film on the whole surface of the specimen; and removing the mask, thereby forming a specified pattern of the electrodes. By this method, it is possible to form electrodes having high adhesion to diamond and diamond film for electronic devices.

Abstract: A method for fabricating submicron T-shaped gates for the field-effect transistors disclosed, which can be accomplished by using a tri-layer positive photoresist with a single electron beam exposure and a single development step. Therefore, the cost can be reduced and the yield can be raised for fabricating high speed field-effect transistors.

Abstract: A method is disclosed for forming crystalline silicon carbide (SiC) semiconductors on a semiconductor-on-insulator (SOI) structure. In this method, the thin silicon layer of an SOI substrate is converted to silicon carbide using a carbonization reaction. The SiC layer is then, optionally, further increased in thickness using a vapor deposition reaction, preferably using a silicon-containing cyclobutane gas. Rather than increasing the thickness of the SiC layer, the vapor deposition process can also be used to deposit a layer of another semiconductor (e.g., a III-N or III-P semiconductor) on the thin SiC layer. The products made by this process are also claimed.

Abstract: An asymmetrical IGFET including a lightly and heavily doped drain regions and an ultra-heavily doped source region is disclosed. Preferably, the lightly doped drain region and ultra-heavily doped source region provide channel junctions.

Abstract: A method of fabricating semiconductor devices including forming a plurality of layers of semiconductor material on the surface of a substrate, forming a mask without using a resist on the layers which can be disassociated in-situ, removing an unmasked portion of the layers to form a semiconductor device with a gate region and opposed exposed source and drain surfaces, selectively growing source and drain contact regions on the exposed source and drain surfaces respectively, the contact regions defining opposed sidewalls adjacent the gate region, disassociating the mask, forming sidewall spacers on the sidewalls, forming a metal contact on the source, drain and gate regions with the spacers preventing intercontact therebetween, and depositing a passivating layer over the semiconductor device, with all of the previous steps being performed in-situ in a modular equipment cluster.

Abstract: A technique for forming a high-performance sub-half micron MOS transistor is disclosed which has improved short channel characteristics without degradation of device performance. The transistor comprises a semiconductor substrate, a gate electrode, graded source and drain impurity regions, a first set of gate sidewall spacers, and a second set of gate sidewall spacers. The graded source and drain impurity regions comprise a relatively linear continuum of doped regions, ranging from lightly doped (LDD) regions, to moderately doped (MDD) regions, to heavily doped regions. Additionally, the transistor may include a punch through barrier region located within the substrate under the gate electrode. With these features, the transistor of the present invention allows for more precise control of conduction channel length without degradation of either (1) body factor and current drive, and/or (2) junction leakage, and without compromising hot carrier immunity.