Abstract: VLSI I/O structures to reduce the effects of simultaneous switching noise (SSN) on output driver circuits and enhance electrostatic discharge immunity, while reducing chip area, in both input receiver circuits and output driver circuits include improved transistors having deep-junction drain and a multi-cascaded, resistive deep-junction source structure.

Abstract: The present invention provides a process for forming an MOS semiconductor device having an LDD structure, which includes a forming a gate electrode by first etching a conductive layer to a certain depth by an RIE process and by second etching the conductive layer by an isotropic plasma etching process. In forming the source/drain of the device, an n.sup.+ source/drain and an n.sup.- source/drain are formed in a sequential manner. The gate line first is formed with its width over-sized compared with its channel length, and finally is formed to its final size.

Abstract: A method for forming a borderless, contact or via hole, has been developed, in which a thin silicon nitride layer is used as an etch stop to prevent attack of an underlying interlevel dielectric layer, during the opening of the borderless, contact or via hole, in an overlying, interlevel dielectric layer. The thin silicon nitride layer is the top layer of an interlevel dielectric composite layer, used between metal interconnect levels.

Abstract: Methods of forming MOS transistors include the steps of forming hot-carrier suppression electrodes on opposing sides of an insulatedgate of a field effect transistor, to reduce hot-carrier degradation parasitics and reduce gate-to-drain overlap capacitance (C.sub.gd). These methods include the steps of forming at least a first hot-carrier suppression electrode between a drain electrode and an insulated gate electrode of a field effect transistor. The hot-carrier suppression electrode reduces the likelihood of hot-carrier degradation parasitics by inhibiting hot electron injection into the gate oxide of the field effect transistor and also reduces the gate-to-drain region capacitance by eliminating the need to establish a fully-overlapped geometry between the transistor's gate and lightly doped drain (LDD) region extension as a way to prevent parasitic injection. According to a preferred embodiment of the present invention, a first electrically insulating layer (e.g., SiO.sub.

Abstract: A mask is used for lightly doped drain and halo implants in an integrated circuit device. The mask exposes only portions of the substrate adjacent to field effect transistor gate electrodes. Since the halo implant is made only near the transistor channels, where it performs a useful function, adequate device reliability and performance is obtained. Since the halo implant is masked from those portions of the active regions for which it is not necessary, active region junction capacitances are lowered. Such lowered capacitances result in an improved transistor switching speed. The mask used to define the lightly doped drain and halo implant region can be easily formed from a straight forward combination of already existing gate and active area geometries.

Abstract: A method of forming apparatus including a force transducer on a silicon substrate having an upper surface, the silicon substrate including a dopant of one of the n-type or the p-type, the force transducer including a cavity having spaced end walls and a beam supported in the cavity, the beam extending between the end walls of the cavity, the method including the steps of: (a) implanting in the substrate a layer of a dopant of said one of the n-type or the p-type; (b) depositing an epitaxial layer on the upper surface of the substrate, the epitaxial layer including a dopant of the other of the n-type or the p-type; (c) implanting a pair of spaced sinkers through the epitaxial layer and into electrical connection with said layer, each of the sinkers including a dopant of the one of the n-type or the p-type; (d) anodizing the substrate to form porous silicon of the sinkers and the layer; (e) oxidizing the porous silicon to form silicon dioxide; and (f) etching the silicon dioxide to form the cavity and beam.

Abstract: Methods of forming integrated circuits containing high and low voltage insulated-gate field effect transistors (IGFET) include the steps of forming first and second insulating layers having unequal thicknesses at first and second locations on a face of a semiconductor substrate, respectively, and then forming first and second gate electrodes on the first and second insulating layers, respectively. Formation of the source and drain regions of a high voltage IGFET is then initiated by implanting first dopants of first conductivity type through the first insulating layer and into the first location, using the first gate electrode as an implant mask. Formation of the source and drain regions (e.g., LDD) of the low voltage IGFET is then initiated by implanting second dopants of first conductivity type into the first and second insulating layers.

Abstract: A method for forming a field effect transistor on a substrate includes providing a wordline on the substrate; providing composite masking spacers laterally outward relative to the wordline, the composite masking spacers comprising at least two different materials; removing at least one of the materials of the composite masking spacers to effectively expose the substrate area adjacent to the wordline for conductivity enhancing doping; and subjecting the effectively exposed substrate to conductivity enhancing doping to form source/drain regions.

Abstract: Methods for wavelength determination of a monochromatic beam are described. The methods involve a detector unit containing at least one variable filter and at least one pair of photo detectors. The detectors have photo sensitive regions with their areas varying with the position in one direction. The wavelength for maximum transmission of the variable filter varies in the same direction. By comparing the photo current values from the two detectors, wavelength of the incident beam is determined. Methods to construct wavelength discrimination junction photo detector pair and double barrier photo detector pair are also given.

Abstract: A method of making a complementary metal oxide semiconductor field effect transistor (CMOSFET) using liquid phase deposition. At first, a P-type silicon substrate is prepared, on which are formed a field oxide layer, a P-well, an N-well and a gate oxide layer. Next, a first polysilicon layer is formed. After doping the first polysilicon, a tungsten silicide layer is formed on the first polysilicon layer. Then, the first polysilicon layer and the tungsten silicide layer are patterned to form the polycide gate electrodes. With a mask shielding the area designated to be the N-channel FET, a P.sup.- type ion implant is performed. Then, a first silicon dioxide layer is formed by liquid phase deposition, followed by an anisotropic etching to form the first sidewall spacers. Then, a P.sup.+ type ion implant is performed. A second silicon dioxide layer is again formed by liquid phase deposition. Now, after removing the mask, an N.sup.- type ion implant is performed using the second silicon dioxide layer as a mask.

Abstract: After forming an n-type active layer, an n.sup.+ -type source region and an n.sup.+ -type drain region at predetermined regions of a GaAs substrate, a silicon oxide film and a silicon nitride film are deposited, and then source and drain electrodes are formed. By effecting overetching on the silicon nitride film using a resist mask formed on the silicon nitride film, an upper layer portion of the silicon oxide film at a gate electrode formation region is removed, and a carrier concentration at the active layer immediately under the gate electrode is reduced. This improves a gate/drain breakdown voltage. Thereafter, a lower layer portion of the silicon oxide film at the gate formation region is removed by wet etching, and the gate electrode is formed at this removed region. A drain breakdown voltage is improved owing to reduction of the carrier concentration only at the surface region of the active layer immediately under the gate electrode.

Abstract: Nickel is introduced to a peripheral circuit section and a picture element section on an amorphous silicon film to crystallize them. After forming gate electrodes and others, a source, drain and channel are formed by doping impurities, and laser is irradiated to improve the crystallization. After that, electrodes/wires are formed. Thereby an active matrix type liquid crystal display whose thin film transistors (TFT) in the peripheral circuit section are composed of the crystalline silicon film crystal-grown in the direction parallel to the flow of carriers and whose TFTs in the picture element section are composed of the crystalline silicon film crystal-grown in the direction vertical to the flow of carriers can be obtained.

Abstract: A Field Effect Transistor (FET) and a method of forming FETs on a silicon wafer. First, trenches are formed in a surface of the silicon wafer. An ONO layer is formed on the surface, lining the trenches. Potassium is diffused along the ONO layer. Part of the ONO layer is removed to expose the wafer surface with the ONO layer remaining in the trenches. A gate oxide is formed on the exposed wafer surface. Finally, FET gates are formed on the gate oxide. Preferably, potassium is introduced during Chem-Mech polish when the trenches are filled with polysilicon. A slurry containing KOH is used to polish the polysilicon and the potassium diffuses from the slurry along the ONO layer. After Chem-Mech polish, the poly in the trenches is recessed by Reactive Ion Etching (RIE) it below the wafer surface. Optionally, after RIE, the wafer may be dipped in a KOH solution. Next, an oxide collar is formed along the ONO layer in the trenches above the recessed polysilicon.

Abstract: A simplified method of manufacturing an active matrix substrate is disclosed. Gate wires, gate electrodes, gate insulating films, an etching stopper layer, semiconductor layers and contact layers are formed on an electrically insulating substrate. Pixel electrode material films, second electrical conductor films and second insulating films are formed successively on the substrate. The second insulating film and the second electrical conductor film are simultaneously patterned, so that source wires, source electrodes and drain electrodes are formed from the second electrical conductor film, and a protective film from the second insulating film. Then, the pixel electrode material film is patterned thereby to form pixel electrodes in a plurality of regions defined by the gate wires and the source wires.

Abstract: A method of forming a resistor from semiconductive material includes, a) providing a substrate; b) providing a layer of semiconductive material over the substrate; c) providing a pair of openings into the semiconductive material layer; d) plugging the pair of openings with an electrically conductive material to define a pair of electrically conductive pillars within the semiconductive material, the pair of pillars having semiconductive material extending therebetween to provide a resistor construction; and e) providing a conductive node to each of the electrically conductive pillars.

Abstract: In a thin film transistor, the reliability, yield and characteristics are improved by preventing the wire breaking of gate electrodes and wirings and the breakdown of a gate insulating film. Materials having at least one element of nickel, iron, cobalt and platinum are selectively formed closely on or beneath an amorphous silicon thin film formed on a substrate, and the materials are selectively crystallized, and the crystallized regions thus obtained are used as a channel forming region and impurity regions of a thin film transistor, and further an isolation between the thin film transistors is performed by the uncrystallized region.

Abstract: The semiconductor device includes (A) a first MOS transistor including (a) a main surface at a part of which recesses are formed, an inner surface of the recesses defining a crystal plane being able to be thermally oxidized at higher speed than the main surface, and (b) an insulator formed on the inner surface of the recesses, the inner surface of the recesses working as a channel region and the insulator working as a gate insulator in the first MOS transistor, and (B) a second MOS transistor in which the main surface works as a channel region and an insulator formed on the main surface works as a gate insulator, the gate insulator of the first MOS transistor having a greater thickness than that of the gate insulator of the second MOS transistor. Thus, above the thinner gate insulator is formed the second MOS transistor, while above the thicker gate insulator is formed the first MOS transistor having a higher breakdown voltage than that of the second MOS transistor.

Abstract: A high density metal gate metal-oxide semiconductor fabrication process to selectively and locally oxidize specific regions of a wafer without increasing the numbers of mask, so as to separately control the thickness of the oxide at the gate, P+ zones and N+ zones, the process including the step of forming a first tye trap zone, the step of forming a shielding layer consisting of an oxide pad and a nitride layer, and the step of forming an oxide layer and removing the nitride layer but the oxide pad to be left before the growing of an insulative oxide layer.

Abstract: In a force sensor, a resonator is mounted by means of a dielectric layer on a bending element. Deformation of the bending element changes the resonant frequency of the resonator.

Abstract: A diffused channel insulated gate field effect transistor comprised of a gate isolation layer and a gate electrode positioned on an upper surface of a semiconductor substrate of a first conductivity type; a body region of a second conductivity type present in the semiconductor substrate lying below a part of the gate electrode, on at least one side thereof, and extending downwards to a first depth; a source region of said first conductivity type present in the body region, spaced away from the first end of the gate electrode, at the upper surface and extending downwards therefrom to a second depth, shallower than the first depth; and a lightly doped region of the first conductivity type present in the body region, at least partly between the source region and the gate electrode, extending downwards to a substantially shallower depth than the second depth.