Abstract: In a semiconductor device, an n.sup.+ -type polysilicon layer is formed on a substrate through a gate oxide layer. A p.sup.+ -type source or drain diffusion layer is formed on both sides of an impurity layer in the substrate. The n.sup.+ -type polysilicon layer is positioned over an intermediate portion of a channel formation layer, and has an oxide layer on an upper surface thereof. The n.sup.+ -type polysilicon layer has at its side portions a p.sup.+ -type polysilicon layer to make a gate electrode together with the n.sup.+ -type polysilicon layer. The gate electrode semiconductor layer is formed on the channel formation layer through the gate insulation layer in such a manner that in a portion contacting with the gate insulation layer, the nearer the portion approaches the impurity layers of the source and drain regions, the larger the work function of the portion becomes.

Abstract: A process of manufacture has the steps of forming a metal film on the insulating substrate, applying photoresist on the metal film, exposing the photoresist to light to form a photoresist pattern by developing, etching the metal film with the photoresist pattern as an etching mask, forming an insulating film on the insulating substrate by making the insulating substrate with the photoresist pattern contact a liquid-phase deposition treatment liquid, and removing the photoresist pattern or the combination of the photoresist pattern and the insulating film thereon. Through these steps, the metal film for use as the metal wiring to effect contact with the electrode of the TFT is buried in the surface of the insulating substrate. Consequently, the resistance of the metal wiring can greatly be reduced. Thereby, it is produced a thin film transistor capable of rendering an large area, large capacity display possible and free from a difference in level.

Abstract: A metal oxide semiconductor field effect transistor includes source and drain regions formed between a gate. The gate comprises a first conductive layer and a second conductive layer formed on the first conductive layer, and the second conductive layer has curved sidewalls with an insulating layer formed adjacent to the sidewalls. The method of making such a transistor improves the fabrication process, since the deposition thickness is controlled rather than the amount of etching. The transistor has a shortened channel width with reduced overlap capacitance, and the LDD doping compensation phenomenon is removed.

Abstract: A process for manufacturing a CMOS device is disclosed.

Abstract: A method of manufacturing a semiconductor device including the steps of: forming an insulating film on an electrical connection area; forming a contact hole in the insulating film; forming a crystalline semiconductor region in the contact hole; forming a wiring layer covering the contact hole; and selectively implanting ions over the wiring layer by using a resist mask to make the crystalline semiconductor region have a high resistance. A semiconductor device having customized wiring connections can be manufactured in a short term.

Abstract: A test apparatus for determining alignment of an implantation mask in the construction of thin film transistors (TFTs), a method for determining the alignment of an implantation mask employed in the construction of TFTs, and a method for constructing TFTs, employing a test implantation mask for the construction of an implantation region for multiple adjacent TFTs, are provided in which the test implantation mask has a sloped or stepped profile such that the masked area increases as the test implantation mask extends from one TFT to another TFT.

Abstract: In forming a thin film transistor (TFT) having an offset structure or a lightly doped drain (LDD) structure, a blocking material having a lower etching rate than that of a material constructing a gate electrode is formed. By using the blocking material as a mask, a gate electrode material is side-etched selectively to form gate electrodes. The blocking material is processed selectively and remains in a drain region side. Also, an offset region or an LDD region is formed under the blocking material by performing an impurity ion implantation. On the other hand, after the gate electrodes are formed, a resist is added and then light exposure is performed from a source region side using a light blocking material as a mask, so that the resist remains in a drain region side of the gate electrode. Also, by implanting an impurity ion, an offset region or an LDD region is formed in the drain region side.

Abstract: A structure of and a method for fabricating a highly sensitive photo sensor. Its structural feature is that a PIN photo diode is allocated in a MOSFET, by means of enlarging the detected small photo current from PIN photo diode by the MOSFET; so as to avoid the shortcoming of conventional PIN photo diode, and enhance the sensitivity of photo sensing.

Abstract: An electrical interconnection method includes: a) providing two conductive layers separated by an insulating material on a semiconductor wafer; b) etching the conductive layers and insulating material to define and outwardly expose a sidewall of each conductive layer; c) depositing an electrically conductive material over the etched conductive layers and their respective sidewalls; and d) anisotropically etching the conductive material to define an electrically conductive sidewall link electrically interconnecting the two conductive layers. Such is utilizable to make thin film transistors and other circuitry.

Abstract: According to the present invention, there is provided a method for fabricating a field effect transistor having reduced hot electron effects. In one embodiment, the method comprises the steps of disposing a gate oxide layer on a semiconductor substrate; disposing a gate material on the gate oxide layer; masking a portion of the gate material; anisotropically etching a gate structure into the gate material such that a trench is formed in the semiconductor substrate; implanting a source structure in the semiconductor substrate, the source structure having a first doping region superjacent a second doping region, the second doping region being lightly doped relative to the first doping region.

Abstract: A process for formation of a thin film transistor which can be usefully applied to a high picture quality active matrix liquid crystal display is disclosed. Particularly, a process for formation of an improved polysilicon thin film transistor is disclosed. In the process for formation of a polysilicon thin film transistor, the solid phase crystallization of a non-crystalline silicon is carried out under a high pressure oxygen atmosphere, and therefore, the solid phase crystallization time for a non-crystalline silicon is shortened so as to improve the productivity, and the grain size of the polysilicon is made more uniform so as improve the electrical characteristics of the TFT (thin film transistor).

Abstract: A method for making semiconductor thin film transistors (TFTs) having a bottom gate such that the gate electrode is formed in a furrow of an insulating layer, with a gate oxide and body polysilicon formed thereon, thereby allowing the source and drain level to be in a smooth plane parallel with the gate level. Steps that may be included in the disclosed method for fabricating thin film transistors having a bottom gate are: a) forming an insulating layer on a substrate, and forming a furrow by etching the insulating layer at a portion corresponding to where a gate line is to be formed; b) forming a gate line in the furrow by depositing a conductive layer, and etching back the conductive layer; c) forming a gate insulator on the gate line, forming a semiconductor layer on the gate insulator; and d) forming impurity regions at opposite sides of the gate line.

Abstract: A method and resulting structure is disclosed for extending or enlarging the effective volumes of one or more source, drain, and/or emitter regions of integrated circuit structures such as an SCR structure and/or an MOS structure designed to protect an integrated circuit structure from damage due to electrostatic discharge (ESD). The additional effective volume allows the SCR and/or MOS protection devices to handle additional energy from an electrostatic discharge applied, for example, to I/O contacts electrically connected to the SCR protection structure. The additional effective volume is obtained, without additional doping or masking steps, by forming individual deep doped regions or wells, beneath one or more heavily doped source, drain, and emitter regions, at the same time and to the same depth and doping concentration as conventional main P wells and/or N wells which are simultaneously formed in the substrate, whereby no additional masks and implanting steps are needed.

Abstract: A polycrystalline silicon film formed of an active layer of a thin film transistor is entirely hydrogenated by a low-temperature process, thereby lowering the resistance and relaxing the electric field in the vicinity of the drain to reduce the leakage current. A gate and an insulating film that covers it are formed on a substrate having an insulating surface. A hydrogenated polycrystalline silicon film is formed over the substrate, including the gate, with the insulating film interposed therebetween. A silicon oxide film pattern is formed on the polycrystalline silicon film directly above the gate. Source/drain regions are formed on the polycrystalline silicon film substantially at two external sides of the silicon oxide film pattern. The source/drain regions are formed from a hydrogen-containing amorphous silicon film, a conductive silicon film and a metal film, which are successively stacked on the polycrystalline silicon film.

Abstract: An infrared sensor array and manufacturing method thereof is disclosed including a substrate; a supporter having a space portion for adiabatic structure between the substrate and supporter; and a plurality of infrared sensors arranged with a predetermined distance each other on the supporter above the space portion.

Abstract: In a vertical power MOSFET having a U-shaped trench gate and a method of manufacturing the same, a P-type base layer and an N.sup.+ -type emitter layer are formed on the surface of an N-type semiconductor substrate. A plurality of trenches are formed to such a depth as to reach the semiconductor substrate. After that, an oxide film and a nitride film are formed in this order on the surface of the resultant element and on the inner surfaces of the trenches. In this case, the oxide film and nitride film are each formed to have a thickness corresponding to the operating characteristics of the element at the stage of design. The nitride film of a gate wiring region is selectively removed to form an oxide film on the surface of the element. Consequently, a thick gate insulation film of the oxide films can be formed between the corner portions of the N.sup.

Abstract: A semiconductor processing method of forming a pair of adjacent field oxide regions includes, i) providing a sacrificial pad oxide layer to a thickness of from 20 Angstroms to 100 Angstroms; ii) providing a patterned masking layer over the sacrificial pad oxide layer and over a desired active area region, the layer having a thickness of from 500 Angstroms to 3000 Angstroms and comprising a pair of adjacent masking blocks having a minimum pitch of from 0.5 micron to 0.7 micron; iii) oxidizing portions of the substrate unmasked by the masking layer in an O.sub.2 ambient at a pressure of at least 15 atmospheres to form at least one pair of adjacent field oxide regions, the ambient being substantially void of H.sub.

Abstract: A semiconductor fabrication process allows for the fabrication of high-voltage transistors, logic transistors, and memory cells where, as required for sub-0.3 micron device geometries, the gate oxide of the logic transistors is thinner than the tunnel oxide thickness of the non-volatile memory cells without the undesirable contamination of the gate oxide of the logic transistors or contamination of the tunnel oxide of the memory cells. In one embodiment, the tunnel oxide of the memory cells is grown to a desired thickness. In a next step, a layer of doped polysilicon which will serve as the floating gate of the memory cell(s) is immediately deposited over the tunnel oxide of the memory cells, thereby protecting the tunnel oxide from contamination in subsequent masking and etching steps. The gate oxide of the logic transistors and the gate oxide of the high-voltage transistors are then grown to a desired thickness.

Abstract: A process for fabricating MOSFET devices, in which performance, as well as reliability enhancements, are included, has been developed. An LDD process, using first an ion implanted phosphorous step, to address hot carrier lifetime phenomena, followed by a arsenic ion implantation step, used to improve device performance, is described.

Abstract: A multicolor organic light emitting device employs vertically stacked layers of double heterostructure devices which are fabricated from organic compounds. The vertical stacked structure is formed on a glass base having a transparent coating of ITO or similar metal to provide a substrate. Deposited on the substrate is the vertical stacked arrangement of three double heterostructure devices, each fabricated from a suitable organic material. Stacking is implemented such that the double heterostructure with the longest wavelength is on the top of the stack. This constitutes the device emitting red light on the top with the device having the shortest wavelength, namely, the device emitting blue light, on the bottom of the stack. Located between the red and blue device structures is the green device structure.