Abstract: A method for fabricating a semiconductor device which is capable of forming an ultra-shallow junction causing no defect in source/drain regions. The method includes the steps of providing a semiconductor substrate formed with n and p type wells and element-isolating films, forming gate oxide films on the n and p type wells, respectively, forming a polysilicon film over the entire exposed upper surface of the resulting structure, implanting first impurity ions having an n type conductivity in a portion of the polysilicon film disposed over the p type well, implanting first impurity ions having a p type conductivity in a portion of the polysilicon film disposed over the n type well, implanting second impurity ions having the p type conductivity in portions of the polysilicon film except for portions which will be used as gate electrodes, annealing the resulting structure in such a manner that the first impurity ions having the p type conductivity are diffused into the n type well, thereby forming p.sup.

Abstract: In a method for manufacturing a thin film transistor, an upper portion of a channel region of an a--Si active layer is selectively etched using the source electrode and the drain electrode as a mask, so as to form a recess in the upper portion of the channel region of the active layer. Hydrogen plasma is irradiated to an exposed surface including a surface of the active layer, and succeedingly, an amorphous silicon film is deposited on the exposed surface including the surface of the active layer, and then patterned so as to form a light block film which also acts a protection layer.

Abstract: A fully planarized concave transistor is produced having a structure, wherein a lightly doped drain(LDD) region and a source/drain region are formed and accumulated on a semiconductor substrate in a predetermined pattern, a thick insulating layer is formed on the surface and the sidewall of the source/drain, a gate formed between the source and drain, with a gate insulating layer is formed between the source and the gate, and between the drain and the gate to insulate therebetween.

Abstract: An image sensor and method of making such sensor is described. The sensor includes an integral color filter array, comprising: a semiconductor substrate having an optically planar top surface; a plurality of spaced image pixels formed in the substrate; and an array of physically contiguous color filter elements embedded in the substrate whose top and bottom surfaces are coplanar and which have no overlap of color filter layers between adjacent color filter elements.

Abstract: A semiconductor processing method of forming a pair of adjacent field oxide regions includes, i) providing a sacrificial pad oxide layer to a thickness of from 20 Angstroms to 100 Angstroms; ii) providing a patterned masking layer over the sacrificial pad oxide layer and over a desired active area region, the layer having a thickness of from 500 Angstroms to 3000 Angstroms and comprising a pair of adjacent masking blocks having a minimum pitch of from 0.5 micron to 0.7 micron; iii) oxidizing portions of the substrate unmasked by the masking layer in an H.sub.2 O steam ambient at a pressure of from about 0.5 atmosphere to about 2 atmospheres and at a temperature of from about 900.degree. C. to about 1200.degree. C.

Abstract: A semiconductor pressure sensor utilizes single-crystal silicon piezoresistive gage elements dielectrically isolated by silicon oxide from other such elements, and utilizes an etched silicon substrate with an etch stop. P-type implants form p-type piezoresistive gage elements and form p+ interconnections to connect the sensor to external electrical devices. The diaphragm is made from epitaxially-grown single-crystal silicon. Passivation nitride can be used for additional dielectric isolation. One practice of the invention provides over-range cavity protection, and thus increased robustness, by forming an over-range stop for the diaphragm through localized oxygen ion implantation and etching.

Abstract: After an interconnection layer of Al alloy or the like is formed on an insulating film covering the surface of a substrate, a contact hole is formed through a laminate of the insulating film and connection layer at the position corresponding to a connection part of the substrate. After the interconnection layer is patterned, an adhesion layer of TiN or the like is formed on the insulating film, covering a left portion of the interconnection layer and the inner surface of the contact hole. A conductive layer of W or the like is formed on the adhesion layer by blanket CVD, burying the contact hole. Thereafter, the conductive layer and adhesion layer are etched back to form an interconnection 22 including the left portion of the interconnection layer, left portions of the adhesion layer, and left portions of the conductive layer. A step of the interconnection can be relieved by leaving the portions of the conductive layer on the side walls of the interconnection.

Abstract: A dual gate insulating film of a thin film transistor (TFT) is disclosed in which edge-thinning is eliminated by forming a thermal oxide film after depositing an oxide film by a low temperature chemical vapor deposition (CVD) method. According to the disclosed dual gate insulating film and method for making the same, exposure of gate material on edges of the gate film is prevented, grooving of the active pattern of polycrystalline silicon is reduced, and the same electric and insulating characteristics as those of the conventional thermal oxide film are obtained.

Abstract: A process for fabricating a deep submicron MOSFET device has been developed, featuring a local threshold voltage adjust region in a semiconductor substrate, with the threshold voltage adjust region self aligned to an overlying polysilicon gate structure. The process consists of forming a narrow hole opening in a dielectric layer, followed by an ion implantation procedure used to place the threshold voltage adjust region in the specific area of the semiconductor substrate, underlying the narrow hole opening. A polysilicon deposition, followed by a chemical mechanical polishing procedure, results in the creation of a narrow polysilicon gate structure, in the narrow hole opening, self aligned to the threshold voltage adjust region.

Abstract: A CMOS device with buried contacts is formed using a polysilicon stack layer and twin-well and liquid phase deposition (LPD) processes. A gate oxide layer and a first polysilicon layer are formed on a substrate. Then the gate oxide and first polysilicon layer are etched to form gate structures. A polysilicon stack layer is formed on the gate structures. The polysilicon stack layer and the first polysilicon layer are anisotropically dry etched, forming first trenches that expose portions of the gate oxide and portions of the substrate defining S/D regions for a NMOSFET. A NMOS lightly doped drain (LDD) with halo doping profile is implanted. A first LPD oxide is selectively formed in the first trenches. Subsequently, a first heavy ion implantation is performed into the polysilicon stack layer for forming the source, drain, gate and buried contacts of the NMOSFET. Trenches are formed in the polysilicon stack layer and first polysilicon layer to define S/D regions and buried contacts for a PMOSFET.

Abstract: A solid state imaging device reduces the occurrence of crosstalk between a plurality of picture elements arranged in a linear or matrix form. The solid state imaging device includes a plurality of photosensitive cells formed on a first principal surface of a semiconductor substrate, a transfer electrode formed in a gap area among the cells on the first principal surface to read out charges produced in the cells, a drive metal wiring formed on the transfer electrode within the gap area, a first insulating film covering the cells with a predetermined thickness, and a plurality of metal reflecting films formed on the first insulating film so that the whole surface of each of the metal reflecting films forms a reflecting surface substantially parallel to a surface of each of the cells on the side of the first principal surface. Light passed through the photosensitive cells from a side opposite to the first principal surface is reflected back to each of the photosensitive cells.

Abstract: High voltage MOS transistors are fabricated contemporaneously with scaled flash EEPROM array transistors. Active silicon regions separated by field oxide isolation structures are formed as in the prior art. A sacrificial thermal oxide layer simultaneously removes Kooi effect residual nitridization and provides gate oxide for the high voltage transistors of a thickness commensurate with the high voltage application. The sacrificial oxide is thereafter removed from all circuit areas except over high voltage device active areas. Growth of tunnel oxide, first polysilicon, interpoly dielectric, peripheral gate oxide and second polysilicon layers as well as patterning of the layers are accomplished in a known manner. The second polysilicon layer is patterned to create lines which lie within lines formed of the first polysilicon layer, the second polysilicon layer aiding controlling the final channel length of the high voltage devices.

Abstract: An improved method of manufacturing active matrix displays with ESD protection through final assembly and in process testing and repair capabilities. At least a first set of shorting bars is formed adjacent the row and column matrix. The shorting bars are respectively coupled to one another in series to allow testing of the matrix elements. A first shorting bar is coupled to the odd row lines, a second shorting bar is coupled to the even row lines, a third shorting bar is coupled to the odd column lines and a fourth shorting bar is coupled to the even column lines. The shorting bars can remain coupled to the matrix through final assembly to provide ESD protection and final assembly and testing capability.

Abstract: A method of forming a resistor from semiconductive material includes, a) providing a substrate; b) providing a layer of semiconductive material over the substrate; c) providing a pair of openings into the semiconductive material layer; d) plugging the pair of openings with an electrically conductive material to define a pair of electrically conductive pillars within the semiconductive material, the pair of pillars having semiconductive material extending therebetween to provide a resistor construction; and e) providing a conductive node to each of the electrically conductive pillars.

Abstract: To efficiently mass-produce back reflectors which are inexpensive and have high reflectivity, the invention provides a manufacturing method for a solar cell comprising at least a metal layer having a texture structure and high reflectivity, a transparent layer, a semiconductor layer, and a transparent electrode which are formed on a substrate, wherein the metal layer consists of at least two layers formed as a first metal layer and a second metal layer. The method includes a step of, after forming the first metal layer, annealing the first metal layer before forming the second metal layer. The invention also provides a solar cell manufacturing apparatus having, upstream of a second metal layer forming chamber, a heating chamber in which the first metal layer can be annealed.

Abstract: A method for forming a CMOS device, with improved yield, performance and reliability characteristics, has been developed. Yield improvements have been addressed by the use of a dual insulator spacer, used to reduce the risk of salicide bridging, as well as the use of pocket implantation regions, used to reduce punchthrough leakage. An ultra shallow junction extension region has been created in a peripheral channel region, reducing the resistance of this region, thus enhancing the performance of the CMOS device. In addition, ultra lightly doped source and drain regions are used to relax reliability concerns, regarding hot electron injection.

Abstract: Disclosed is a method for making a high-temperature super-conducting field-effect transistor with a thick super-conducting channel, the method comprising the steps of depositing a template layer on an oxide crystal substrate by using a pulse laser depositing apparatus; forming a YBa.sub.2 Cu.sub.3 O.sub.7-x layer on the template layer; patterning the YBa.sub.2 Cu.sub.3 O.sub.7-x layer to form a patterned YBa.sub.2 Cu.sub.3 O.sub.7-x layer having an opening and expose a surface portion of the template layer; depositing a YBa.sub.2 Cu.sub.3 O.sub.7-x channel layer on the surface portion of the template layer and over the patterned YBa.sub.2 Cu.sub.3 O.sub.7-x layer, the channel layer having a thickness of from 60 to 100 nm; sequentially forming an SrTiO.sub.3 protective layer and an SrTiO.sub.

Abstract: Method for fabricating a semiconductor device is disclosed, including the steps of: forming a first resist layer on a substrate; patterning a predetermined region of the first resist layer to form a pattern having a first width which exposes the substrate; forming an insulating film on an entire surface of the substrate including the first resist layer; forming a second resist layer on the insulating film; patterning a predetermined region of the second resist layer to form a pattern over the pattern of the first resist layer having a second width which exposes the insulating film; using the second resist layer as a mask in etching the exposed insulating film to form sidewall spacers at sides of the pattern of the first resist layer; forming a metal layer on an entire resultant surface including the second photoresist layer; and, removing the first and second resist layers and the insulating film to form a T form gate electrode.

Abstract: An object of the technology of our invention is to solve a luminance defect viewed as a "seam" or the like and to provide a liquid crystal display device having a screen for equally displaying an image. For example, when an exposing process is performed for one conductor layer or a dielectric layer, a total of four photomasks are used corresponding to four shot areas. A light insulation layer of a photomask used for the exposing process for patterning for example a signal line is formed so that it becomes a projection pattern of the signal line. The photomasks corresponding to adjacent shot areas are formed so that patterns of the light insulation layers of the boundary portion are engaged with each other on the plane.

Abstract: A fabrication method and resultant electronic module having one or more surfaces enhanced with interconnects and components. Electronic modules having, for example, resistors and capacitors integral with a side surface thereof are disclosed. Further described are electronic modules with interconnects electrically attaching for example, side to side, or side to end surfaces are described. Moreover, discussion of an electronic module having a Silicon Front Face chip is contained herein. Specific details of the fabrication method, resulting electronic module, and related wafer processing are set forth.