Abstract: A method for making a variable length LDD spacer structure is disclosed. A first insulation layer (i.e., gate oxide) is formed on a semiconductor device having a P-well and an N-well provided in a substrate. A first and a second polysilicon gate are formed on the P-well and the N-well respectively wherein the first insulation layer is interposed between the wells and the gates. A second insulation layer is formed over the first and second gates. N-type impurity ions are selectively implanted to form lightly doped N-type diffusion regions in the P-well. Similarly, P-type impurity ions are selectively implanted to form lightly doped P-type diffusion regions in the N-well. A polysilicon spacer is formed on both side walls of each of the gates. Each spacer covers a portion of the lightly doped N-type and P-type diffusion regions. N-type impurity ions are selectively implanted in a portion of the lightly doped N-type diffusion regions not covered by the spacers.

Abstract: A method of manufacturing thin film transistors for use in a liquid crystal display which reduces the failures due to excessive leakage current. A silicon layer, first insulating layer, and gate electrode layer are serially formed over a transparent substrate. The gate electrode layer is patterned to form a plurality of gate electrodes and associated pairs of gate line electrodes, and the silicon layer is patterned into thin-film transistor regions. Then, a relatively thick second insulating layer is formed over the substrate, and contact holes are formed in the second insulating layer. Finally, a metal layer is formed and patterned over the second insulating layer and through the contact holes to connect each gate electrode with its associated pair of gate line electrodes; and to form source and drain electrodes.

Abstract: A process for fabricating dual-gate CMOS of semiconductor devices having in-situ nitrogen-doped polysilicon by rapid thermal chemical vapor deposition in a rapid thermal reactor is disclosed. The process comprises the steps of first fabricating components of the dual-gate CMOS on a semiconductor silicon substrate. The dual-gate CMOS components includes P- and N-wells and source/drain regions formed in the silicon substrate. Gate oxide for the dual-gate CMOS is then grown. A thin nitrogen-doped polysilicon film is then deposited over the gates, and followed by the deposition of a undoped polysilicon film, which covers over the surface of the thin nitrogen-doped polysilicon film. Ions are then implanted into the dual-gates CMOS. In the process, the thin nitrogen-doped polysilicon film is deposited by introducing SiH.sub.4 and NH.sub.3 gas mixture into the rapid thermal reactor under a pressure of about 0.4 torr at about 750.degree. C. The thin nitrogen-doped polysilicon film has a thickness of about 60 .ANG..

Abstract: A thin film electronic imager device has a repaired area between an upper conductive layer and an underlying component in the array in which portions of the upper conductive layer and a dielectric layer have been removed such that the upper conductive layer is electrically isolated from the underlying component. The repaired area has a bottom level having a surface comprising material of the underlying component and an intermediate step level having a surface comprising the dielectric layer material that extends around the periphery of the repaired area. The lateral dimension of the intermediate step level is greater than the lateral dimension of the bottom level such that the width of the intermediate level step surface is in the range between about 1 .mu.m and 3 .mu.m. Formation of the structure in the repair area is done by removing material by laser ablation to set back the upper conductive layer from the sidewall of the dielectric material in the region in which the defect was excised.

Abstract: A method is provided for improving the performance characteristics of the MOS devices contained within an integrated circuit that has been subjected to a rapid thermal anneal. After the rapid thermal anneal the integrated circuit is heated for more than about 30 minutes at a temperature of more than about 430.degree. C. in a gaseous atmosphere that contains hydrogen, typically forming gas.

Abstract: A novel method of fabricating a double-gate MOSFET structure is disclosed. The method utilizes selective lateral epitaxial growth of silicon into a thin gap formed between two sacrificial dielectric films for accurate thickness control. The sacrificial films are then replaced by a gate material (e.g., polysilicon) such that top and bottom gates are self-aligned to each other and to the channel region. Also disclosed is a self-aligned double-gate MOSFET constructed in accordance with the foregoing method.

Abstract: A liquid crystal display having a gate insulating film of whose dielectric constant is a high and exhibits excellent leakage characteristics, includes a plurality of gate wirings formed on the transparent substrate, a plurality of signal lines arrayed to intersect the plurality of gate wirings, a plurality of switching devices located at the point of intersection between the respective gate wirings and signal lines. The switching device comprises a gate electrode constituted by aluminum or an aluminum alloy and a gate insulating film inserted between the channels of switching devices and the gate electrode. The gate insulating film has a first anodic oxide film constituted by aluminum or an aluminum alloy and a second anodic oxide film constituted by tantalum or a tantalum alloy. In the manufacturing method thereof, metals, aluminum or tantalum, are simultaneously anodically oxidized so as to suppress a hillock.

Abstract: The antifuse structure of the present invention includes a bottom planarized electrode, an ILD disposed over the bottom electrode, an antifuse cell opening in and through the ILD exposing the bottom electrode, a first barrier metal layer disposed by means of collimated sputter deposition in the antifuse cell opening to form a layer of uniform thickness existing only within the antifuse cell opening in order to protect the antifuse material layer from diffusion from the bottom electrode and to form an effective bottom electrode of reduced area, hence reducing the capacitance of the device, an antifuse material layer disposed in the antifuse cell opening and over the first barrier metal layer, a second barrier metal layer disposed over the antifuse material layer and optionally formed by collimated sputter deposition, and a top electrode disposed over the second barrier metal layer.

Abstract: A field effect transistor (10) has an active layer (16) formed in a substrate (12). A gate (20) is disposed on an elevated platform (18) formed from the active layer (16). The elevated platform (18) raises the bottom surface (21) of the gate (20) relative to the top surface (34, 36) of the active region (13) on either side of the gate (20). A fabrication method for the transistor (10) forms the elevated platform (18) by etching the active region surface (44) on both sides of the gate (20) so that the bottom surface (21) of the gate (20) is elevated relative to the top surface (34) of the surrounding active region (13). The gate (20) itself and/or a patterned photoresist layer (116) may be used as a mask for performing this etch.

Abstract: A semiconductor device comprises a piezoresistive pressure sensor (12), which has a membrane (14), which is constituted by a conducting epitaxy layer (16), which is applied to a conducting semiconductor substrate (18) of the opposite conductivity. On the outer surface (20) of the membrane facing away from the semiconductor substrate (18) at least one piezoresistor (22) is incorporated. Between the semiconductor substrate (18) and the epitaxy layer (16) an annularly structured intermediate layer (28) is incorporated, which defines a region (26'), adjoining the inner surface (24) of the membrane, of an opening (26) extending through the semiconductor substrate (18). This opening (26) is produced by anisotropic semiconductor etching, the intermediate layer (28) having a conductivity which is opposite to that of the semiconductor substrate so that this intermediate layer (28) functions as an etch stopping means and is not attacked by the etchant.

Abstract: A semiconductor processing method of forming a field oxide region on a semiconductor substrate includes, a) providing a patterned first masking layer over a desired active area region of a semiconductor substrate, the first masking layer having at least one side edge; b) providing a silicon sidewall spacer over the side edge of the patterned first masking layer, the silicon sidewall spacer having a laterally outward projecting foot portion; c) oxidizing the substrate and the silicon sidewall spacer to form a field oxide region on the substrate; d) stripping the first masking layer from the substrate; and e) providing a gate oxide layer over the substrate. The invention enables taking advantage of process techniques which minimize the size of field oxide bird's beaks without sacrificing upper field oxide topography.

Abstract: A superlattice of LT-GaAs layers and another semiconductor layers such as LT-AlGaAs or HT-GaAs is grown on a substrate. Lattice imperfectness such as strain or crystal defects is selectively introduced. Then, the superlattice is annealed to produce As precipitates at selected locations of the LT-GaAs layers. When strain is given by metal electrodes, anisotropic etching and self-alined metal deposition can be done utilizing these electrodes. Various semiconductor devices, particularly SET device can be manufactured utilizing those metallic precipitates.

Abstract: A suspended microstructure process assembly includes a first microstructure assembly, with a temporary substrate having a first surface and a first microstructure fabricated on the first surface; a second microstructure assembly, including a final substrate having a second surface and a second microstructure fabricated on the second surface; connecting elements for joining the first microstructure assembly to the second microstructure assembly with a predetermined separation and alignment; and a removable bond temporarily securing the first microstructure assembly to the second microstructure assembly until the temporary substrate is removed. The connecting elements may be electrically conductive contacts or electrically nonconductive spacers. Electrically conductive contacts may be supplied to the first microstructure from a back side of the first microstructure assembly. The first microstructure fabricated on the first surface may incorporate a removable layer to enable multiple level suspended structures.

Abstract: A manufacturing method of a semiconductor device includes the steps of depositing a metallic film (light-shielding film), an insulating film and a semiconductor film in this order on an insulating substrate, and after patterning the insulating film and the semiconductor film in a predetermined shape, oxidizing an exposed region of the metallic film using the insulating film and the semiconductor film as a mask. As a result, the light-shielding film composed of the metallic film is formed so as to cover the semiconductor film to block light from an external portion. The manufacturing method permits a process of forming a resist pattern for use in forming the light-shielding film and a process of etching the light-shielding film to be omitted, thereby reducing the required number of processes. Moreover, as a level difference is not generated around the light-shielding film, a generation of a level difference on the semiconductor film can be prevented.

Abstract: A process has been developed in which photoresist thinning at the edges of silicon chips, resulting from photoresist flowing from semiconductor chips, exhibiting features with raised topographies, to flat scribe regions, has been reduced. The reduction in photoresist flowing has been accomplished by creating a chessboard pattern of raised insulator and metal features, in the scribe line region, thus reducing the differences in topography between the scribe line and chip regions. The areas between the raised mesas, in the scribe line regions, are used for laser or optical endpoint detection of RIE processes.

Abstract: In a semiconductor strain sensor, for example, using resistors of a polycrystalline semiconductor material such as polycrystalline silicon as strain gauges, the sum of the temperature coefficient of resistance (TCR) of the resistor and the temperature coefficient of strain sensitivity (TCK) is adjusted not by controlling the impurity carrier concentration but by controlling the resistivity, thereby an output fluctuation due to a change in the temperature can be suppressed.

Abstract: A method for passivating diamond films to substantially prevent them from oxidizing at temperatures up to 800.degree. C. in an oxygen atmosphere. The method involves depositing one or more passivating layers over the diamond film wherein one of the layers is nitride and the other layer is quartz. The passivation technique is directly applicable to diamond sensor pressure transducers and enable them to operate at temperatures above 800.degree. C. in oxygen environments. The passivation technique also provides an economical and simple method for patterning diamond films.

Abstract: A process is disclosed for fabricating a CMOS structure with ESD protection. The outside transistors are covered with a protective oxide layer which is so masked as to cover the areas of the respective source and drain regions adjoining the field-oxide regions and the gate regions. The protective oxide layer is then subjected to a heat treatment, after which a siliciding process is carried out.

Abstract: A semiconductor device and manufacturing method wherein a gate insulating film is formed on a semiconductor substrate. A gate is formed on the gate insulating film and a sidewall spacer is formed on respective sides of the gate. The substrate is etched at the respective sides of the gate to form respective recessed parts of the substrate. An insulating film is provided on the recessed parts of the substrate and the recessed parts are filled with a semiconductor layer. Impurity regions are formed contacting the semiconductor layer in the semiconductor substrate on the respective sides of the gate.

Abstract: An MOS transistor for use in an integrated circuit, particularly CMOS integrated circuits, is fabricated with a self-aligning contact and interconnect structure which allows for higher packing density. Self-aligning source and drain contacts overlap the gate but are prevented from short circuiting to the gate by oxide insulation between the source/drain contacts and the gate, and a layer of silicon nitride above the gate. Contacts to the gate are made on top of the gate over the active region of the transistor because the source and drain regions are protected by a hardened layer of photoresist during etching of insulation to expose the gate contact. Source, drain and gate contacts are protected by a layer of titanium silicide so that interconnects are not required to completely cover these areas. Low resistance interconnects are formed of titanium silicide encapulated by a thin film of titanium nitride.