Abstract: A method of producing a semiconductor device having a LDD structure using a semiconductor substrate laminated with an insulating film, a polysilicon layer, and a first conductive layer where the first conductive layer is formed of a high melting point metal and the first conductive layer and polysilicon layer are removed in the region other than a gate pattern formation region but without exposing the insulating layer. After implanting the semiconductor substrate with a first impurity, the residual polysilicon layer in the region other than the gate pattern formation region along with a polysilicon layer sidewall in the gate pattern formation region are converted into a silicon oxide layer by subjecting to oxidation treatment, and the semiconductor substrate is laminated with a second conductive layer.

Abstract: In the manufacture of a large-area electronic device (e.g. an active-matrix liquid-crystal display or other flat panel display), a TFT of improved lifetime stability results from the inclusion of a field-relief region (22) which is of lower doping concentration than the drain region (12) and which is formed in an area (2) of lateral separation between the channel region (21) and the drain region (22). An energy beam (40), e.g. from an excimer laser, is used to provide the field-relief region (22), by laterally diffusing the doping concentration of the drain region (12) along an area (2) of the semiconductor film (20) significantly larger than the thickness of the semiconductor film (20). The method is simple and easily controllable, an advantageous doping profile (FIG. 3b) is obtained along the field-relief region (22) by this lateral diffusion.

Abstract: Integrated circuits employing titanium nitride are significantly improved by using a specific method for formation of the titanium nitride in the device fabrication. In particular, a plasma such as one formed in an electron cyclotron resonance apparatus is employed to dissociate a source of nitrogen and a source of hydrogen and the dissociation products are combined at the integrated circuit deposition substrate with titanium tetrachloride. The resulting deposition is essentially devoid of chlorine and has advantageous step-coverage properties.

Abstract: In forming a thin film transistor (TFT) having an offset structure or a lightly doped drain (LDD) structure, a blocking material having a lower etching rate than that of a material constructing a gate electrode is formed. By using the blocking material as a mask, a gate electrode material is side-etched selectively to form gate electrodes. The blocking material is processed selectively and remains in a drain region side. Also, an offset region or an LDD region is formed under the blocking material by performing an impurity ion implantation. On the other hand, after the gate electrodes are formed, a resist is added and then light exposure is performed from a source region side using a light blocking material as a mask, so that the resist remains in a drain region side of the gate electrode. Also, by implanting an impurity ion, an offset region or an LDD region is formed in the drain region side.

Abstract: The present invention is directed to a unique method for fabricating a silicon based MOS transistor having an inverse-T refractory metal gate structure. The gate fabricated according to this invention comprises a main CVD tungsten portion and a lower sputtered tungsten portion outwardly extending from the bottom of the CVD portion such that a cross section of the gate appears as an inverted "T". A Cl.sub.2 /O.sub.2 plasma etch is used to etch the CVD tungsten layer and a chemical etch is used to etch the sputtered tungsten layer to form the gate electrode. It has been discovered that sputtered tungsten is more resistant to Cl.sub.2 /O.sub.2 reactive ion etch than is CVD tungsten. The sputtered tungsten layer acts as a shield to protect the underlying gate oxide layer from ion damage throughout the fabrication process.

Abstract: In a method for manufacturing an LDD type semiconductor device, an insulating layer is formed on a semiconductor substrate of a first conductivity type, and an opening is formed in the insulating layer. Then, a first sidewall insulating layer is formed on a sidewall of the insulating layer, and a gate insulating layer is formed on the semiconductor substrate. Then, a gate electrode is buried in the opening. Then, the first sidewall insulating layer is removed, and impurities of a second conductivity type are introduced into the semiconductor substrate to form a low concentration impurity region in the semiconductor substrate. Then, the insulating layer is removed, and a second sidewall insulating layer is formed on a sidewall of the gate electrode. Finally, impurities of the second conductivity type are introduced into the semiconductor substrate to form a high concentration impurity region in the semiconductor substrate.

Abstract: The breakdown characteristics of a lateral transistor integrated in an epitaxial layer of a first type of conductivity grown on a substrate of an opposite type of conductivity and comprising a drain region formed in said epitaxial layer, are markedly improved without recurring to critical adjustments of physical parameters of the integrated structure by forming a buried region having the same type of conductivity of the substrate and a slightly higher level of doping at the interface between the epitaxial layer and the substrate in a zone laying beneath the drain region of the transistor.

Abstract: A method of manufacturing a semiconductor device includes the steps of forming an interconnection layer consisting of a metal material on a substrate, and forming an anti-reflection film including a compound having metal-silicon-oxygen on this interconnection layer using the same metal material as the material used for this interconnection layer. Thus, it is made possible to form interconnection layer and anti-reflection film by the same apparatus and it is also made possible to treat interconnection layer and anti-reflection film with the same etchant. As a result, efficiency in the method of manufacturing the semiconductor device including an anti-reflection film can be improved.

Abstract: A structure and method for forming contact structures in integrated circuits. A buffer layer is formed over an underlying conductive element. A first conductive layer is then deposited over the buffer layer and patterned to define a first interconnect layer. While the first interconnect layer is patterned, the buffer layer protects the underlying conductive element from damage. Portions of the buffer layer which are not covered by the first interconnect layer are then removed, and a second conductive layer is deposited over the integrated circuit. The second conductive layer is then anisotropically etched to form conductive sidewall spacers alongside the vertical sidewalls of the first interconnect layer, where at least one of the conductive sidewall spacers makes electrical contact with the underlying conductive element. Therefore, a conductive contact is made between the underlying conductive element and the first interconnect layer through at least one of the conductive sidewall spacers.

Abstract: This invention relates to a method for making sealed cavities on silicon wafer surfaces by anodic bonding and with electrically insulated conductors through the sealing areas to connect functional devices inside the cavities to electrical terminals outside said cavities. Said conductors are provided by the use of doped buried crossings in a single crystal silicon substrate, thereby also allowing different kinds of integrated silicon devices, e.g. sensors to be made. Further, the invention relates to a device made by the novel method.

Abstract: In producing a top gate type insulated gate semiconductor device in which a non-single crystalline semiconductor layer is used to form a channel forming region, after a gate electrode is formed on the non-single crystalline semiconductor layer through a gate insulating film, while ultraviolet light is irradiated to the non-single crystalline semiconductor layer, heating treatment is performed at a temperature of from 300.degree. to 600.degree. C. in an atmosphere containing nitrogen oxide or hydrogen nitride, in order to neutralize a recombination center in the non-single crystalline film or a boundary between the non-single crystalline film and the gate insulating film.

Abstract: In an active matrix electroluminescent display, a pixel containing a grounded conductive electric field shield between an EL cell and the switching electronics for the EL cell. In a method of fabricating the pixel, first, an EL cell switching circuit is formed, then an insulating layer is formed over the switching circuit and a conductive layer (the field shield) is formed over the insulating layer. A through hole is provided in the field shield such that an electrical connection can be made between the switching circuit and an EL cell. The EL cell is then conventionally formed on top of the shield layer. Consequently, the shield isolates the switching circuit from the EL cell and ensures that any electric fields produced in the EL cell do not interfere with the operation of the switching electronics. Furthermore, the switching circuitry for each cell contains two transistors; a low voltage MOS transistor and a high voltage MOS transistor.

Abstract: Disclosed is a process for fabricating a semiconductor device having both a functional region and an electrostatic discharge (ESD) protective region formed on the same substrate. A gate oxide layer is formed on both the functional region and the ESD protective region and a polysilicon layer is formed on the gate oxide layer. A mask is used to etch the polysilicon layer and the gate oxide layer to form gate electrode and also expose part of the silicon substrate. Ions are implanted to form a lightly doped source/drain electrode. An ESD mask is used to selectively remove part of the oxide layer on the functional region, thus forming an isolator on lateral sides of the gate electrode in the functional region. Ions are then implanted to form a heavily doped region and lightly doped source/drain electrode. After that, a metallization layer is formed by sputtering deposition and then rapid thermal annealing and etching are performed to form self-aligning TiSi.sub.

Abstract: The base zones of MOSFETs and IGBTs are generated by implanting dopants of the second conductivity type into the surface of a first layer of the first conductivity type, and a second layer of the first conductivity type is deposited thereon. During the deposition, the dopants diffuse up to the surface of the second layer and form base zones. The base zones are thereby provided with a laterally expanded region of high conductivity under the surface through which the minority carriers can flow off to the source electrode with low voltage drop.

Abstract: There is provided a semiconductor device with very small functional elements, which can be constructed by necessary minimum components without any unnecessary surface area, thus being capable of significantly reducing the layout area and adapted for achieving a fine geometry and a high level of integration. The semiconductor device is provided with a first semiconductor area of a first conductive type (for example a p.sup.- well) and a second semiconductor area formed on or under the first semiconductor area and having a second conductive type different from the first conductive type (for example a source or drain area), in which an electrode electrically connected to the first semiconductor area is formed through the second semiconductor area, and the first and second semiconductor areas are shortcircuited by the above-mentioned electrode.

Abstract: High voltage MOS transistors are fabricated contemporaneously with scaled flash EEPROM array transistors. Active silicon regions separated by field oxide isolation structures are formed as in the prior art. A sacrificial thermal oxide layer simultaneously removes Kooi effect residual nitridization and provides gate oxide for the high voltage transistors of a thickness commensurate with the high voltage application. The sacrificial oxide is thereafter removed from all circuit areas except over high voltage device active areas. Growth of tunnel oxide, first polysilicon, interpoly dielectric, peripheral gate oxide and second polysilicon layers as well as patterning of the layers are accomplished in a known manner. The second polysilicon layer is patterned to create lines which lie within lines formed of the first polysilicon layer, the second polysilicon layer aiding controlling the final channel length of the high voltage devices.

Abstract: A method for the determination of the resistivity of an n-type epitaxial layer formed on a silicon substrate is disclosed. This invention resides in either directly determining the true resistivity of a sample by preparing this sample without a natural oxide film which is responsible for the change with the passage of time or indirectly determining the true resistivity of a sample by intentionally forming on the sample a natural oxide film so stable to defy the change with the passage of time and measuring resistivity of this sample.

Abstract: First through fourth wiring layers are formed on the surface of a silicon substrate, then a silicon oxide layer containing fluorine is deposited over the wiring layers and the silicon substrate, and then another silicon oxide layer containing no fluorine is deposited over the silicon oxide layer containing fluorine. Subsequently, the silicon oxide layer containing no fluorine is flattened by polishing it for a predetermined length of time when the silicon oxide layer containing no fluorine is polished, the silicon oxide layer containing fluorine serves as a stopper, since the polishing rate of the silicon oxide layer containing fluorine is lower than that of the silicon oxide layer containing no fluorine.

Abstract: A process for fabricating CMOS devices has been developed, in which decreased cycle time has been achieved, via a reduction in photomasking steps. The low cycle time CMOS process features the use of only one photo mask to create both the lightly doped, as well as the heavily doped N type, source and drain regions, by performing both implantations, after creation of the insulator sidewall spacer. In addition the P type source and drain regions are formed, using an oxide layer as a blockout for the P well region, thus eliminating the use of another photomasking procedure.

Abstract: The present invention provides a method of manufacturing twin wells in a silicon substrate which uses only one photo step and provides a smooth surface topology. The first embodiment begins by forming spaced field oxide regions in the substrate. The spaced field oxide regions define a first region and a second region. A masking layer composed of borophosphosilicate glass (BPSG) and a barrier layer are formed over the field oxide regions. The barrier layer and the masking layer over the first region are removed by a photo etch process. Then, N-type impurities are implanted into the first region forming a n-well using the barrier layer and masking layers as a mask. Then, p-type impurities are implanted into the substrate to form a p-type layer beneath the N-well and a P-well in the second region. The barrier layer and the masking layer are then removed. The substrate is then annealed to drive in the ion implanted impurities thereby forming a n-well and a p-well.