Abstract: On an insulating film (12) covering the surface of a semiconductor substrate (10), a gate electrode layer (14), a gate insulating film (16), and a semiconductor layer (18) such as silicon are sequentially deposited to form an under-gated MOS transistor. A flat coating film such as resist is formed covering the semiconductor layer (18). The coating film is then etched back to expose the surface of the semiconductor layer (18) at the area above the gate electrode layer (14). The left coating film is used as the mask for the selective growth of a mask material layer (24) such as tungsten on the exposed surface of the semiconductor layer (18) with a side-projection. After removing the left coating film, impurity ions such as BF2 are selectively injected in the semiconductor layer (18) using the mask material layer (24) as the mask to form a source region (18S) and a drain region (18D).

Abstract: In a method for fabricating a FET of the present invention, first and second side walls are formed on a side surface of a gate electrode, and two n-GaAs layers are formed on an active layer by selective growth using the side walls as a mask. After that, the side walls are removed, whereby double recesses are formed around the gate electrode.

Abstract: A MOSFET comprising a gate oxide layer on a silicon substrate, a polysilicon gate formed on the gate oxide layer, the width of which gradually widens going from bottom to top, a side gate oxide layer formed by an oxidation process surrounding the polysilicon gate, the side gate oxide layer also gradually widening from bottom to top, a source/drain region beside the gate oxide layer, a connection element having a stacked structure of an oxide layer and a polysilicon or polycide layer on the field oxide, a doped polysilicon side wall beside the side gate oxide layer and making electric connection between the source/drain region and the connection element.

Abstract: A high electron mobility transistor is disclosed, which takes advantage of the increased mobility due to a two dimensional electron gas occurring in GaN/Al.sub.x Ga.sub.1-x N heterojunctions. These structures are deposited on basal plane sapphire using low pressure metalorganic chemical vapor deposition. The electron mobility of the heterojunction is approximately 620 cm.sup.2 per volt second at room temperature as compared to 56 cm.sup.2 per volt second for bulk GaN of the same thickness deposited under identical conditions. The mobility of the bulk sample peaked at 62 cm.sup.2 per volt second at 180.degree. K. and decreased to 19 cm.sup.2 per volt second at 77.degree. K. The mobility for the heterostructure, however, increased to a value of 1,600 cm.sup.2 per volt second at 77.degree. K. and saturated at 4.degree. K.

Abstract: A fabrication method for semiconductor devices connecting a multi-crystal semiconductor thin film and a semiconductor region including a high density of an impurity formed in a single crystal semiconductor substrate. After forming a N-type semiconductor region as the emitter by ion implanting, for instance, as into a P-type semiconductor region as the base, a polysilicon thin film 114 is deposited so as to be implanted with As ions and then heat treated. In this case, an amorphous portion of the N-type semiconductor region and an amorphous silicon thin film in contact therewith are transformed by solid phase epitaxial growth so as to form a single crystal semiconductor region, a single-crystalline silicon thin film, and a polysilicon thin film, thus forming a bipolar element having an emitter.

Abstract: A method of forming substrate vias in a GaAs wafer begins with a GaAs wafer in which all top side processing steps are complete. The top surface of the GaAs wafer includes top surface via contacts, which are in electrical contact with the bottom surface ground plane once the ground vias are complete. A protective layer is formed on the top surface of the wafer to protect the finished integrated circuitry. A portion of the substrate is removed from the bottom surface to achieve a thin layer of substrate material. The bottom surface of the thinned substrate is metalized with a first metal layer. Laser via holes are drilled into the thinned substrate from the bottom surface of the wafer to within a few microns from the top surface metal via contacts. The laser holes are drilled by emitting a controlled number of single pulses over the selected via location.

Abstract: Disclosed is an improved metal oxide-semiconductor field-effect transistor having two diffused regions extending apart from under one and the other edge of the gate in the opposite directions, at least one of the diffused regions being composed of a first leastdoped, short section, a second lightly-doped, short section, and a third heavily-doped, long section. Either diffused region may be used as drain. The series-connection of least and lightly-doped sections of the same longitudinal size or depth improves the current driving capability of the semiconductor device. Also, methods of making such MOSFETs are disclosed.

Abstract: An integrated circuit has a semiconductor die with a substrate and at least first and second bond pads. An internal circuit is fabricated on the semiconductor die and connected to the first bond pad. An electrostatic discharge protection circuit including cascaded bipolar transistors is connected in series with a field effect transistor between the first and second bond pads. In another version, an output buffer of the integrated circuit is divided into sections. An electrostatic discharge protection circuit is triggerable in response to a voltage in the substrate. Resistive connections are provided from the sections of the output buffer to one of the bond pads. The output buffer is operative upon an electrostatic discharge event to inject sufficient charge into the substrate to produce the voltage to trigger the electrostatic discharge protection circuit. Other circuits, devices, systems and methods are also disclosed.

Abstract: There are disclosed a semiconductor device having electrical elements buried a SOI substrate and a manufacturing method thereof, the manufacturing method of the invention comprising the steps of: (a) forming a first isolating insulator layer at a seed wafer by using an isolation mask, depositing a second isolating insulator layer overlying the first isolating insulator layer and the seed wafer, and defining contact holes by using a contact mask to form contacts on the seed wafer; (b) depositing a first polysilicon layer on the second isolating insulator layer and the contacts and doping an impurity into the first polysilicon layer; (c) patterning the first polysilicon layer to define an electrical element, depositing an insulating layer around the electrical element, and forming a second polysilicon layer overlying the second isolating insulator layer and the insulating layer; (d) doping an impurity into the second polysilicon layer for connecting with a handling wafer, and polishing the second polysilicon la

Abstract: In a method of making a tunable twin guide (TTG) type tunable semiconductor laser, over the surface of a semiconductor substrate of one conductivity type, an active layer, a central layer of the opposite conductivity type, and a tuning layer, each being stripe-shaped and overlying the top of the preceding one is provided. This method is characterized in that the processing of semiconductor elements for defining the current path/optical waveguide inside the laser is carried out not by etching but by using selective epitaxy method such as metal organic vapor phase epitaxy (MOVPE). The use of selective MOVPE permits to form stripe-shaped layers at high precision and good uniformity, with consequent effects of minimizing scattering of laser light, increasing the efficiency of the drive power to laser light output conversion and enhancing the coupling efficiency with optical fibers. Besides thinner central layer that can be formed can contributes to enlarging the tunable bandwidth of laser light.

Abstract: A conductivity modulation type MOSFET (IGBT) including an n-type high resistance layer, p-type base regions selectively formed in a first major surface of the high resistance layer, n-type source regions formed in the surface of each base region, a p.sup.+ well region formed in a central region of each of the base regions, a channel in the base region between one of the n-type source regions and the high resistance layer, a gate electrode formed above the channel, an emitter electrode formed in contact with the p.sup.+ well region and the n-type source region, a gate insulating film formed between the gate electrode and the channel, and a metal electrode formed in contact with a second major surface of the high resistance layer opposite the first major source, the electrode forming a Schottky barrier junction.

Abstract: A method of producing a thin film field effect transistor. An insulating thin film layer is formed on a gate electrode subsequent to the gate electrode being formed on a substrate. A multilayer structure is formed on the insulating thin film layer subsequent to the insulating thin film layer being formed on the gate electrode by alternately laminating a number of non-monocrystalline semiconductor material layers and a number of non-monocrystalline material layers.

Abstract: A new method of metallization of an integrated circuit is described. Semiconductor device structures are fabricated in and on a semiconductor substrate. At least one contact opening to the semiconductor substrate and at least one lithography alignment cross mark opening structure are formed. A barrier layer is preferably sputtered within the contact openings and over the semiconductor device structures. A cold aluminum seed layer is sputtered over all surfaces of the contact openings. Next, a hot aluminum flow layer is provided to obtain the desired step coverage of the contact openings. A second cold aluminum layer is then sputtered onto the hot aluminum layer to define the edges of the wide lithography alignment marks while maintaining good contact opening coverage.

Abstract: A method and an apparatus for connecting a semiconductor chip to a carrier system, wherein the semiconductor chip that is already detached but is still situated in the wafer union and that is held on a self-adhesive foil is detached therefrom and move onto a prescribed connecting location on the carrier system and connected thereto. The placement of the semiconductor chip onto the carrier system involves considerably less expenditure of time and capital outlay than the prior art systems. The carrier system is provided with a joining material at the prescribed connecting locations. The wafer union on the self-adhesive foil is aligned such that the surface of a semiconductor chip to be connected lies opposite the location of the carrier system that is provided with the joining material. The semiconductor chip in the wafer union is brought to a spacing of .ltoreq.0.

Abstract: A conductive layer is formed beneath a runner in an integrated circuit. The conductive layer is also formed within vias. The conductive layer preserves electrical connection should the runner separate due, perhaps, to electromigration or stress voiding. The conductive layer also provides protection against various failures or defects which may occur in the runner material within the vias.

Abstract: Source (51) and drain (52) of a thin-film transistor (TFT) are formed from a conductive layer (5) using a photolithographic step (FIG. 3) in which the gate (4) serves as a photomask. In accordance with the invention the insulated gate structure (3,4) is formed at the upper face of the channel-forming semiconductor film (2), i.e. remote from the transparent substrate (1). The semiconductor film (2) may be annealed to high-mobility polycrystalline material before depositing the gate structure (3,4) and the overlying conductive layer (5). In this way, high speed TFTs can be formed due to a combination of low gate-to-drain and gate-to-source capacitances and the provision of the transistor channel in the high quality semiconductor material adjacent to the upper face of the film (2). Preferably ultra-violet radiation (20: FIG.

Abstract: A semiconductor laser device of an AlGaInP system includes a GaAs substrate and a surface of the substrate is inclined by 5.degree. or more from a {100} plane in a <011> direction.

Abstract: A method of manufacturing a heterojunction bipolar transistor is disclosed. On a base layer of a first semiconductor which contains at least one of gallium and arsenic as a constituent element, an emitter layer of a second semiconductor is formed which contains as a constituent element at least one of gallium and arsenic and which has a band gap larger that of the first semiconductor. Predetermined regions of the emitter layer and an upper portion of the base layer are removed to form a mesa structure. Then, a surface of a junction region of the base layer and the emitter layer of the formed mesa structure is treated using a phosphate etchant and a sulfur or sulfide passivating agent. After the surface treatment, the surface of the junction is covered with an insulating film.

Abstract: A method for cleaving semiconductor devices along planes accurately positioned. Resist is applied to a major surface of the semiconductor device and a mask is projected upon the resist covered major surface. The mask is opaque in those regions in which no cleave is desired. Following the exposure of the resist, the removal of the mask and the development of the resist, an ion beam is positioned incident upon the semiconductor surface such that ion beam etching occurs in the areas in which no resist covers the semiconductor structure. Once a sufficient depth is etched in the areas not covered with resist such that the strength of the semiconductor structure in those areas is significantly less than in those areas covered by resist, the ion beam etching process is ended and the resist is stripped from the semiconductor structure. Subsequently, force is applied within the area in which the ion beam etching occurred to cleave the semiconductor structure within that region.

Abstract: A method of fabricating self aligned static induction transistors. The method comprises fabricating an N silicon on N.sup.- silicon substrate having an active area. A guard ring is formed around the active area. An N.sup.+ polysilicon layer is formed that comprises source and gate regions. An oxide layer is formed on the N.sup.+ polysilicon layer. A second polysilicon layer is formed on the oxide layer. A second oxide layer is formed on the second polysilicon layer which is then masked by a self aligning mask. Trenches are etched into the substrate using the self aligning mask and gate regions are formed at the bottom of the trenches. A first layer of metal (gate metal) is deposited to make contact with the gate regions. A layer of photoresist is deposited and planarized, and the first layer of metal is overetched below the top surface of the trench. Plasma nitride is deposited and planarized, and a polysilicon mask is deposited over the planarized layer of plasma nitride.