Abstract: A display substrate, a manufacturing method thereof, and a display device are provided. The display substrate includes: a base substrate; an anode structure, disposed on the base substrate; a light emitting layer, disposed on a side of the anode structure away from the base substrate; and a cathode layer, disposed on a side of the light emitting layer away from the base substrate, the anode structure includes a reflective layer and an inorganic layer disposed on a side of the reflective layer away from the base substrate, the cathode layer includes a transflective layer, and the inorganic layer is configured to adjust a distance between the reflective layer and the transflective layer.

Abstract: A device has an active area made of an array of first type of device cells and a gate or shield contact area made of an array of a second type of device cells that are laid out at a wider pitch than the array of first type of device cells. Each first type of device cell in the active area includes a trench that contains a gate electrode and an adjoining mesa that contains the drain, source, body, and channel regions of the device. Each second type of device cell in the gate or shield contact area includes a trench that is wider and deeper than the trench in the first type device cell.

Abstract: Microfabrication of a collection of transistor types on multiple transistor planes in which both HV (high voltage transistors) and LV (low-voltage transistors) stacks are designed on a single substrate. As high voltage transistors require higher drain-source voltages (Vds), higher gate voltages (Vg), and thus higher Vt (threshold voltage), and relatively thicker 3D gate oxide thicknesses, circuits made as described herein provide multiple different threshold voltages devices for both low voltage and high voltage devices for NMOS and PMOS, with multiple different gate oxide thickness values to enable multiple transistor planes for 3D devices.

Abstract: An OLED display includes: a color resistor layer, a buffer layer covering the color resistor layer, a transistor having a transparent conductive layer, a gate metal layer, and an output electrode, a pixel electrode, and a storage capacitor having a first transparent electrode and a second transparent electrode. The pixel electrode is the second transparent electrode, a projected area of the first transparent electrode on the substrate is larger than or equal to a projected area of the color resistor layer on the substrate. The upper electrode and lower electrode of the storage capacitor are replaced with a transparent material to raise the aperture rate. The gate insulating layer is used in the capacitor area to increase the capacitance. The storage capacitor adopts the transparent electrodes to solve the issues of low capacitance of the storage capacitor and the unstable components caused by the reflected light.

Abstract: A semiconductor device according to the present disclosure includes first gate-all-around (GAA) devices in a first device area and second GAA devices in a second device area. Each of the first GAA devices includes a first vertical stack of channel members, a first gate structure over and around the first vertical stack of channel members, and a plurality of inner spacer features. Each of the second GAA devices includes a second vertical stack of channel members and a second gate structure over and around the second vertical stack of channel members. Two adjacent channel members of the first vertical stack of channel members are separated by a portion of the first gate structure and at least one of the plurality of inner spacer features. Two adjacent channel members of the second vertical stack of channel members are separated only by a portion of the second gate structure.

Abstract: A semiconductor device according to an embodiment includes a first gate-all-around (GAA) transistor and a second GAA transistor. The first GAA transistor includes a first plurality of channel members, a first interfacial layer over the first plurality of channel members, a first hafnium-containing dielectric layer over the first interfacial layer, and a metal gate electrode layer over the first hafnium-containing dielectric layer. The second GAA transistor includes a second plurality of channel members, a second interfacial layer over the second plurality of channel members, a second hafnium-containing dielectric layer over the second interfacial layer, and the metal gate electrode layer over the second hafnium-containing dielectric layer. A first thickness of the first interfacial layer is greater than a second thickness of the second interfacial layer. A third thickness of the first hafnium-containing dielectric layer is smaller than a fourth thickness of the second hafnium-containing dielectric layer.

Abstract: Embodiments of the disclosure provide an array substrate and a manufacturing method thereof, and a display panel. The array substrate includes a base substrate, and a plurality of sub-pixel areas arranged on the base substrate and arranged in arrays, wherein each sub-pixel area includes an electrode structure, a function layer and a blocking layer arranged on the base substrate in sequence; the function layer includes a plurality of accommodating cavities arranged spaced with each other; the blocking layer is lyophobic and includes through holes in one-to-one corresponding to the accommodating cavities one by one; each sub-pixel area in the structure of the above array substrate includes a plurality of uniformly distributed accommodating cavities, and a charged solution is filled into the accommodating cavities.

Abstract: A full-color display and techniques for fabrication thereof are provided. The display includes first and second continuous independently addressable organic emissive layers disposed over a single substrate or between two substrates or portions of a flexible substrate. The use of continuous emissive layers of a limited number of colors allows for a relatively high resolution display to be achieved without the use of fine metal masks or similar components.

Abstract: A resistive random access memory is provided. The resistive random access memory includes a substrate, a first electrode formed on the substrate, a second electrode formed on the substrate and located on one side of the first electrode, a first metal oxide layer formed on sidewalls of the second electrode, a first control layer formed between the first electrode and the first metal oxide layer, and a second control layer formed on the first control layer and located between the first electrode and the first metal oxide layer.

Abstract: An optoelectronic semiconductor chip includes a rear side with a center and with two contact points for electrical contacting of the semiconductor chip, the contact points being spaced apart from one another, and two solder pads arranged on the contact points, wherein the center is located in a region between the contact points, the solder pads protrude from the rear side and are exposed, and on average, the solder pads are thicker further away from the center than in the vicinity of the center or vice versa.

Abstract: A diode and method of design the layout of the same having reduced parasitic capacitance is disclosed. In particular, the diode for providing fast response protection of an RF circuit from a high power noise event, such as an ESD, voltage spike, power surge or other noise is disclose. The parasitic capacitance in disclosed circuit is a greatly reduced compared to the prior art, thus significantly increasing the speed of the response to dissipate all high power noise events.

Abstract: (a) Loading a substrate into a process chamber; (b) supplying a processing gas including H2O-containing radicals to the substrate; (c) supplying a gas including a halogen element; (d) supplying a gas including one or both of an oxygen element and a nitrogen element after (c); and (e) repeating (c) and (d) are provided.

Abstract: A semiconductor device includes a substrate and a buffer layer disposed on a first portion, a second portion, and a third portion of the substrate. The semiconductor device further includes a multilayer light-emitting diode (LED) stack disposed on the first portion of the substrate, and an optical sensor disposed on the second portion of the substrate. The semiconductor device further includes at least one electrode disposed on the third portion of the substrate, a first conductor in contact with the multilayer LED stack, and a second conductor in contact with the optical sensor. The at least one electrode, the first conductor, and the second conductor are formed of a glassy carbon material.

Abstract: An opto-electronic device includes: a first electrode; an organic layer disposed over the first electrode; a nucleation promoting coating disposed over the organic layer; a nucleation inhibiting coating covering a first region of the opto-electronic device; and a conductive coating covering a second region of the opto-electronic device.

Abstract: An opto-electronic device includes: a first electrode; an organic layer disposed over the first electrode; a nucleation promoting coating disposed over the organic layer; a nucleation inhibiting coating covering a first region of the opto-electronic device; and a conductive coating covering a second region of the opto-electronic device.

Abstract: An apparatus comprising a memory array comprising wordlines, digit lines, and memory cells, with each memory cell coupled to an associated wordline and an associated digit line. Each memory cell comprises a monocrystalline silicon material adjacent to an access device, a monocrystalline metal silicide material directly contacting the monocrystalline semiconductor material, a metal material directly contacting the monocrystalline metal silicide material, and a storage device adjacent to the metal material. Electronic devices, electronic systems, and methods of forming an electronic device are also disclosed.

Abstract: A method for forming a semiconductor device is provided. The method includes providing a substrate having a scribe line, forming a sensing pixel array in the substrate, forming a plurality of transparent pillars over the substrate, and forming a light shielding layer over the substrate and the transparent pillars. The sensing pixel array has a plurality of sensing pixels, and each of the transparent pillars is correspondingly disposed on one of the sensing pixels of the sensing pixel array. The method further includes performing a first cutting process to form an opening directly above the scribe line, while leaving the remaining material covering the scribe line, and performing an etching process along the opening to remove the remaining material until the scribe line is exposed.

Abstract: A magnetic memory device contains a synthetic antiferromagnetic (SAF) structure that includes an antiferromagnetically coupled stack and a reference layer. The antiferromagnetically coupled stack contains plural multilayer stacks. Each multilayer stack contains at least one ferromagnetic material layer, a non-magnetic layer and a non-magnetic SAF spacer layer having a different composition than the non-magnetic layer.

Abstract: Semiconductor device and the manufacturing method thereof are disclosed. An exemplary semiconductor device comprises a fin substrate having a first dopant concentration; an anti-punch through (APT) layer disposed over the fin substrate, wherein the APT layer has a second dopant concentration that is greater than the first dopant concentration; a nanostructure including semiconductor layers disposed over the APT layer; a gate structure disposed over the nanostructure and wrapping each of the semiconductor layers, wherein the gate structure includes a gate dielectric and a gate electrode; a first epitaxial source/drain (S/D) feature and a second epitaxial S/D feature disposed over the APT layer, wherein the gate structure is disposed between the first epitaxial S/D feature and the second epitaxial S/D feature; and an isolation layer disposed between the APT layer and the fin substrate, wherein a material of the isolation layer is the same as a material of the gate dielectric.

Abstract: A transparent display panel with a light-transmitting substrate, a plurality of top-emitting micro light emitting diodes, a plurality of bottom-emitting micro light emitting diodes, and a light shielding layer. The light transmissive substrate has a surface. These top-emitting micro light emitting diodes and these bottom-emitting micro light emitting diodes are disposed on the surface of the light transmissive substrate. The bottom-emitting micro light emitting diodes has an epitaxial structure and a light shielding member, the epitaxial structure has a pair of upper and lower surfaces on the opposite sides, the lower surface faces toward the light transmissive substrate, and the light shielding member is disposed on the upper surface to shield the light emitted by the bottom-emitting micro light emitting diodes towards the upper surface.