Patents Examined by Michelle Mandala
  • Patent number: 11289682
    Abstract: An OLED display device includes a first substrate including a plurality of sub-pixels each including an emission area and a non-emission area; organic light emitting diodes on the first substrate; a second substrate opposed to the first substrate; a black matrix and a color filter layer on one side of the second substrate; a spacer on the black matrix and overlapping or parallel to one of the plurality of the gate lines and the plurality of data lines; and a film layer on the spacer, wherein an air gap is provided between the second substrate and the film layer, and a part of the film layer is exposed by the air gap.
    Type: Grant
    Filed: March 25, 2020
    Date of Patent: March 29, 2022
    Assignee: LG DISPLAY CO., LTD.
    Inventors: Han-Sun Park, Won-Hoe Koo, Ji-Hyang Jang
  • Patent number: 11289533
    Abstract: A method of fabricating a sensing apparatus is disclosed. The method includes providing a substrate that includes a plurality of image sensors, forming an optical filtering film on the substrate, and forming a collimator on the optical filtering film. The method further includes forming a blocking layer on the collimator and forming an illumination layer on the blocking layer. The illumination layer is configured to illuminate an object placed above the illumination layer. The image sensors are configured to detect a portion of light reflected from the object.
    Type: Grant
    Filed: August 31, 2020
    Date of Patent: March 29, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chin-Min Lin, Cheng San Chou
  • Patent number: 11282764
    Abstract: A power module includes a spacer block, a thermally conductive substrate coupled to one side of the spacer block, and a semiconductor device die coupled to an opposite side of the spacer block. The spacer block includes a solid spacer block and an adjacent flexible spacer block. An inner portion of the device die is coupled to the solid spacer block, and an outer portion of the semiconductor device die is coupled to the adjacent flexible spacer block.
    Type: Grant
    Filed: February 7, 2020
    Date of Patent: March 22, 2022
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Liangbiao Chen, Yong Liu, Tzu-Hsuan Cheng, Stephen St. Germain, Roger Arbuthnot
  • Patent number: 11282904
    Abstract: The present disclosure provides an organic light emitting diode (OLED) display device, method of manufacturing the OLED display device, and an electronic device. Using an isolation portion for isolating a first light emitting device layer located at a side of the isolation portion closed to the display region from a second light emitting device layer located at a side of the isolation portion closed to the a through-hole. And using an encapsulation layer covering the light emitting device layer, the isolation portion, and the substrate to make the OLED display device has a high screen ratio while having good package reliability.
    Type: Grant
    Filed: May 15, 2019
    Date of Patent: March 22, 2022
    Inventors: Ming Zhang, Jie Yang
  • Patent number: 11276663
    Abstract: An electronic module has a first substrate 11, a first conductor layer 12 that is provided on one side of the first substrate 11, a first electronic element 13 that is provided on one side of the first conductor layer 12, a second electronic element 23 that is provided on one side of the first electronic element 23, and a second connecting body 70 that has a second head part 71 provided on one side of the second electronic element 23 and an extending part 75 extending from the second head part 71 to the other side and abutting against the first substrate 11 or the first conductor layer 12.
    Type: Grant
    Filed: May 19, 2017
    Date of Patent: March 15, 2022
    Assignee: SHINDENGEN ELECTRIC MANUFACTURING CO., LTD.
    Inventors: Kosuke Ikeda, Osamu Matsuzaki
  • Patent number: 11276722
    Abstract: A method of manufacturing a solid-state image sensor, includes forming a first isolation region of a first conductivity type in a semiconductor layer having first and second surfaces, the forming the first isolation region including first implantation for implanting ions into the semiconductor layer through the first surface, forming charge accumulation regions of a second conductivity type in the semiconductor layer, performing first annealing, forming an interconnection on a side of the first surface of the semiconductor layer after the first annealing, and forming a second isolation region of the first conductivity type in the semiconductor layer, the forming the second isolation region including second implantation for implanting ions into the semiconductor layer through the second surface. The first and second isolation regions are arranged between the adjacent charge accumulation regions.
    Type: Grant
    Filed: July 29, 2020
    Date of Patent: March 15, 2022
    Assignee: Canon Kabushiki Kaisha
    Inventor: Mineo Shimotsusa
  • Patent number: 11276741
    Abstract: The present disclosure discloses a display substrate and a display device. The package structure of the display component includes: a base substrate, a display component arranged on a surface of the base substrate, and a package layer covering the display component, in which the display component includes a display area and a peripheral area surrounding the display area, and the peripheral area is provided with a signal line pattern having an inclined side along a direction perpendicular to an extending direction of the signal line pattern with a slope angle of less than 90 degrees.
    Type: Grant
    Filed: May 29, 2019
    Date of Patent: March 15, 2022
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventor: Chunping Long
  • Patent number: 11264594
    Abstract: The present disclosure provides a display substrate and a manufacturing method thereof, and a display device. The display substrate includes a stretchable base substrate; a display functional layer provided on the stretchable base substrate, the display functional layer including a plurality of pixel structures spaced apart from each other, each of the pixel structures including at least one inorganic insulation layer; the pixel structure having an upper surface distal to the stretchable base substrate and a first lateral surface connected between the upper surface and the stretchable base substrate; a protection layer covering at least a portion of the first lateral surface of at least one of the pixel structures corresponding to the inorganic insulation layer.
    Type: Grant
    Filed: October 23, 2019
    Date of Patent: March 1, 2022
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Huijuan Zhang, Pinfan Wang
  • Patent number: 11264438
    Abstract: An organic light-emitting diode (OLED) display panel includes: a base substrate; one or more thin-film transistor (TFT) structures provided over the base substrate; a planarization layer provided over the TFT structures; anodes provided on an upper surface of the planarization layer; a pixel defining layer provided over the planarization layer defining a plurality of pixel regions, wherein each anode includes an upper surface being exposed in each of the pixel regions; an organic functional layer provided over the anodes; and a cathode provided over the organic functional layer; wherein a sheet resistance of the portion of the anodes that is proximal to the pixel defining layer is smaller than a sheet resistance of the portion of the anodes that is opposite from the pixel defining layer.
    Type: Grant
    Filed: April 9, 2019
    Date of Patent: March 1, 2022
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventor: Wenjun Hou
  • Patent number: 11264345
    Abstract: A method for forming a direct hybrid bond and a device resulting from a direct hybrid bond including a first substrate having a first set of metallic bonding pads, preferably connected to a device or circuit, capped by a conductive barrier, and having a first non-metallic region adjacent to the metallic bonding pads on the first substrate, a second substrate having a second set of metallic bonding pads capped by a second conductive barrier, aligned with the first set of metallic bonding pads, preferably connected to a device or circuit, and having a second non-metallic region adjacent to the metallic bonding pads on the second substrate, and a contact-bonded interface between the first and second set of metallic bonding pads capped by conductive barriers formed by contact bonding of the first non-metallic region to the second non-metallic region.
    Type: Grant
    Filed: April 12, 2019
    Date of Patent: March 1, 2022
    Assignee: INVENSAS BONDING TECHNOLOGIES, INC.
    Inventor: Paul M. Enquist
  • Patent number: 11264312
    Abstract: An object of the present invention is to achieve both securing an insulation distance and securing a chip mounting area in a non-insulated power module. A non-insulated power module includes a plurality of die pads, a plurality of semiconductor chips mounted on upper surfaces of the plurality of die pads, and a package sealing the semiconductor chips, in which lower surfaces of the plurality of die pads are exposed from a lower surface of the package, on the lower surface of the package, first grooves are formed in areas between the plurality of die pads, and the plurality of die pads have a trapezoidal cross-sectional shape in the thickness direction, in which an area of an upper surface is larger than an area of the lower surface.
    Type: Grant
    Filed: July 17, 2020
    Date of Patent: March 1, 2022
    Assignee: Mitsubishi Electric Corporation
    Inventor: Hiroyuki Nakamura
  • Patent number: 11257782
    Abstract: A method of manufacturing a semiconductor device comprising embedding electrodes in insulating layers exposed to the joint surfaces of a first substrate and a second substrate, subjecting the joint surfaces of the first substrate and the second substrate to chemical mechanical polishing, to form the electrodes into recesses recessed as compared to the insulating layers, laminating insulating films of a uniform thickness over the entire joint surfaces, forming an opening by etching in at least part of the insulating films covering the electrodes of the first substrate and the second substrate, causing the corresponding electrodes to face each other and joining the joint surfaces of the first substrate and the second substrate to each other, heating the first substrate and the second substrate joined to each other, causing the electrode material to expand and project through the openings, and joining the corresponding electrodes to each other.
    Type: Grant
    Filed: May 1, 2018
    Date of Patent: February 22, 2022
    Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
    Inventor: Eiichiro Kanda
  • Patent number: 11245055
    Abstract: Disclosed herein are techniques for reducing the pitch between light-emitting diodes (LEDs) in an array of LEDs. According to an aspect of the invention, a device includes an array having a plurality of LEDs and a reflector that is in Ohmic contact with at least two adjacent LEDs of the plurality of LEDs. Each LED of the plurality of LEDs includes a p contact, and the reflector is physically separated from the p contact of each LED of the plurality of LEDs.
    Type: Grant
    Filed: October 23, 2019
    Date of Patent: February 8, 2022
    Assignee: FACEBOOK TECHNOLOGIES, LLC
    Inventors: Daniel Bryce Thompson, James Small
  • Patent number: 11245433
    Abstract: Devices and methods related to radio-frequency (RF) filters on silicon-on-insulator (SOI) substrate. In some embodiments, an RF device can include a silicon die such as an SOI die including a first side and a second side. The silicon die can further include a plurality of vias, with each via configured to provide an electrical connection between the first side and the second side of the silicon die. The RF device can further include at least one RF flip chip mounted on the first side of the silicon die. The silicon die can include, for example, an RF circuit such as a switch circuit, and the RF flip chip can include, for example, a filter such as a surface acoustic wave (SAW) filter.
    Type: Grant
    Filed: March 15, 2020
    Date of Patent: February 8, 2022
    Assignee: Skyworks Solutions, Inc.
    Inventor: James Phillip Young
  • Patent number: 11244922
    Abstract: Provided is a semiconductor device stabilizing bond properties between an electrode terminal provided on a case and an internal wiring connected to a semiconductor element. A semiconductor device includes a base part, a semiconductor element, an electrode terminal, an insulating block, and an internal wiring. The semiconductor element is mounted on the base part. The electrode terminal is held by a case surrounding an outer periphery of the semiconductor element. An end portion of the electrode terminal protrudes toward an inner side of the case. The insulating block is provided on the base part between the semiconductor element and the case. In the internal wiring, one end portion is bonded to the end portion of the electrode terminal on the insulating block, and part of a region extending from the one end portion to the other end portion is bonded to the semiconductor element.
    Type: Grant
    Filed: May 28, 2020
    Date of Patent: February 8, 2022
    Assignee: Mitsubishi Electric Corporation
    Inventors: Takumi Shigemoto, Shohei Ogawa
  • Patent number: 11239282
    Abstract: The present disclosure provides a pixel structure and a fabrication method thereof, a display substrate and a display apparatus. The pixel structure includes a plurality of first pixel portions arranged in a plurality of rows and a plurality of columns, and a second pixel portion that spaces the plurality of first pixel portions from each other. Each first pixel portion includes a plurality of first sub-pixels having a same color and arranged around a center of the first pixel portion. The second pixel portion includes a plurality of second sub-pixels. For four first pixel portions in two adjacent rows and two adjacent columns, each of four regions that are centrosymmetric and obtained by connecting centers of the four first pixel portions to each other corresponds to one pixel unit, and each pixel unit includes two first sub-pixels respectively in two first pixel portions and at least one second sub-pixel.
    Type: Grant
    Filed: January 3, 2018
    Date of Patent: February 1, 2022
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventor: Donghui Yu
  • Patent number: 11233011
    Abstract: An object of the present invention is to improve assemblability of a power semiconductor device. A power semiconductor device includes a plurality of submodules that includes a semiconductor element interposed between a source conductor and a drain conductor, a sense wiring that transmits a sense signal of the semiconductor element, and an insulating portion at which the sense wiring and the sense conductor are arranged, and a source outer conductor that is formed to surround the source conductor and is joined to the source conductor in each of the plurality of submodules. Each source conductor included in the plurality of submodules includes protrusion portions that are formed toward the sensor wiring from the source conductor, are connected to the sense wiring, and define a distance between the sense wiring and the source outer conductor.
    Type: Grant
    Filed: February 7, 2019
    Date of Patent: January 25, 2022
    Assignee: HITACHI ASTEMO, LTD.
    Inventors: Takashi Hirao, Haruka Shimizu
  • Patent number: 11232973
    Abstract: A semiconductor device and a method of fabricating a semiconductor device, the device including a semiconductor substrate that includes a trench defining an active region; a buried dielectric pattern in the trench; a silicon oxide layer between the buried dielectric pattern and an inner wall of the trench; and a polycrystalline silicon layer between the silicon oxide layer and the inner wall of the trench, wherein the polycrystalline silicon layer has a first surface in contact with the semiconductor substrate and a second surface in contact with the silicon oxide layer, and wherein the second surface includes a plurality of silicon grains that are uniformly distributed.
    Type: Grant
    Filed: December 27, 2019
    Date of Patent: January 25, 2022
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Dong-Hyun Im, Kibum Lee, Daehyun Kim, Ju Hyung We, Sungmi Yoon
  • Patent number: 11233215
    Abstract: A display substrate, a manufacturing method thereof, and a display device are provided. The display substrate includes: a base substrate; an anode structure, disposed on the base substrate; a light emitting layer, disposed on a side of the anode structure away from the base substrate; and a cathode layer, disposed on a side of the light emitting layer away from the base substrate, the anode structure includes a reflective layer and an inorganic layer disposed on a side of the reflective layer away from the base substrate, the cathode layer includes a transflective layer, and the inorganic layer is configured to adjust a distance between the reflective layer and the transflective layer.
    Type: Grant
    Filed: November 24, 2017
    Date of Patent: January 25, 2022
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventor: Can Zhang
  • Patent number: 11227946
    Abstract: A device has an active area made of an array of first type of device cells and a gate or shield contact area made of an array of a second type of device cells that are laid out at a wider pitch than the array of first type of device cells. Each first type of device cell in the active area includes a trench that contains a gate electrode and an adjoining mesa that contains the drain, source, body, and channel regions of the device. Each second type of device cell in the gate or shield contact area includes a trench that is wider and deeper than the trench in the first type device cell.
    Type: Grant
    Filed: March 20, 2020
    Date of Patent: January 18, 2022
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Prasad Venkatraman, Dean E. Probst