Abstract: Systems and methods for systems and methods for generating the complete set of IC design layout clips, or any part of the complete set, satisfying usefulness criteria and of a prespecified size. A method includes generating an initial set of integrated circuit (IC) design layout clips as a current set of IC design layout clips. The method includes removing any of IC design layout clips from the current set of IC design layout clips that do not meet the one or more usefulness criteria. The method includes, while a size of the IC design layout clips is less than a desired clip size, generating a new set of IC design layout clips from the current set of IC design layout clips according to every combination of pairs of the design layout clips in the current set of IC design layout clips, and repeating the removing process.

Abstract: A method for increasing coverage of a scan test, executed by at least one processor, includes following operations: analyzing a first netlist file and a second netlist file to acquire a change of a circuit structure, in which the first netlist file corresponds to a first scan chain circuitry, and the second netlist file corresponds to a second scan circuitry wherein the second netlist file is generated by processing the first netlist file with executing an engineering change order (ECO); repairing the second scan chain circuitry according to at least one predetermined criterion; evaluating a candidate node of the repaired second scan chain circuitry, to connect a new flip flop circuit generated after executing the ECO to the candidate node; and storing the second netlist file being processed as a third netlist file, to fabricate an integrated circuit.

Abstract: The disclosure provides integrated circuit (IC) layouts and methods to form the same. An IC layout may include two standard cells, with a well contact cell laterally between them. The well contact cell may include a single semiconductor region having the first doping type, an active bridge region within the single semiconductor region, extending continuously from the first active region of the first standard cell to the third active region of the second standard cell. A doped tap region within the single semiconductor region is laterally separated from the active bridge region. The doped tap region is laterally aligned with the second active region and the fourth active region.

Abstract: Methods for reticle enhancement technology (RET) include inputting a target wafer pattern, where the target wafer pattern spans an entire design area. The entire design area is divided into a plurality of tiles, each tile having a halo region surrounding the tile. A proposed mask for the entire design area is iterated until the proposed mask meets criteria towards producing the target wafer pattern. Each iteration includes calculating a predicted wafer pattern for a subset of the plurality of tiles; and updating the proposed mask for that tile; where all tiles in the subset are calculated before the next iteration.

Abstract: The present disclosure provides a charging system, a power adapter and a charging method. The power adapter includes a first rectifier, a switch unit, a transformer, a second rectifier, a first current sampling circuit, a first capacitor bank and a second capacitor bank, and a control unit. The control unit is configured to output a control signal to the switch unit, and determine an output current of the power adapter according to a current sampling value sampled by the first current sampling circuit when the power adapter enters a first charging mode, wherein, the control unit is configured to isolate the first capacitor bank when the output current of the power adapter is at a rising edge or a falling edge, and enable the first capacitor bank to work when the output current of the power adapter is at a platform segment.

Abstract: Among other things, one or more systems and/or techniques for harvesting thermal energy for utilization by a dispensing system are provided herein. The dispensing system may comprise one or more thermal scavenging devices configured to collect thermal energy from a user. For example, a first thermal scavenging device, coupled to a top housing portion of the dispensing system, may collect thermal energy from a palm of a user hand; a second thermal scavenging device, coupled to a bottom housing portion of the dispensing system, may collect thermal energy from a top portion of the user hand; and/or other thermal scavenging devices may be operatively coupled to the dispensing system. In this way, the collected thermal energy is transformed into electrical energy for powering the dispensing system (e.g., powering a current dispense event, stored for a subsequent dispense event, validation of a refill container, detection of a user, etc.).

Abstract: A method of manufacturing an integrated circuit in which a semiconductor device is provided includes simulating electrical characteristics of the semiconductor device according to a received process variable, by using a model parameter file including a plurality of model parameters, generating semiconductor device layout data based on a result of the simulation, and manufacturing the integrated circuit according to a semiconductor device layout based on the semiconductor device layout data, wherein the plurality of model parameters are stored in the model parameter file in a form of at least one function regarding the process variable.

Abstract: A method for producing a winding assembly for an electro-mechanical device, wherein the winding assembly comprises a circuit board with conductor tracks, wherein the winding assembly preferably comprises a substantial number of optimizable design parameters, the method comprising: optimizing, in a computerized optimization tool, the design of the winding assembly; manufacturing the circuit board with the winding conductor tracks according to the optimized design of the winding assembly; forming the winding assembly of the electro-mechanical device with the manufactured circuit board. The design of the winding assembly is optimized depending on at least one of eddy current losses, hysteresis losses, aerodynamical losses and mechanical losses.

Abstract: A battery protection integrated circuit which is used to construct a system configured to serially communicate among a plurality of the battery protection integrated circuits, the battery protection integrated circuit includes: a higher-level transmission terminal; a lower-level reception terminal; an acquisition device configured to acquire transmission information to transmit to the higher-level circuit; and a storage configured to store at least one of transmitted information transmitted from the lower-level circuit and the transmission information acquired by the acquisition device, the battery protection IC being configured to transmit, in response to reception of instructive information indicating an instruction for the higher-level circuit to read the transmitted information, one of the transmitted information and the transmission information from the higher-level transmission terminal to the higher-level circuit, and simultaneously receive, by the lower-level reception terminal, transmitted informatio

Abstract: Disclosed approaches for processing a circuit design include providing access to checkpoint data of a design checkpoint of a circuit design and starting child processes by a parent process. An initial intermediate representation is generated by the parent process, and concurrent with the generating of the initial intermediate representation, the child processes load the checkpoint data into respective memory spaces. The parent process produces incremental updates to the design checkpoint. The parent process signals availability of the incremental updates to the child processes, which apply the incremental updates to the checkpoint data in the respective memory spaces. The child processes process the circuit design in response to completion of producing incremental updates by the parent placer process.

Abstract: An integrated circuit includes an active zone extending in a first direction, and a spacer extending in a second direction perpendicular to the first direction. The spacer protrudes into a substrate and divides the active zone into a first part and a second part. The integrated circuit includes a first conductive segment and a second conductive segment each extending in the second direction and in a middle layer between the substrate and a metal layer. The first conductive segment forms conductive contact with an active region of a first transistor in the first part of the active zone, and the second conductive segment forms conductive contact with an active region of the second transistor in the second part of the active zone. The spacer joins the first conductive segment and the second conductive segment while electrically isolating the first conductive segment from the second conductive segment.

Abstract: A sparse routing coil structure for a magnetic coil in a wireless charging system is disclosed. The sparse routing coil structure may include a magnetic coil routed by turns of a wire and a turn spacing S between adjacent turns of the wire. The turn spacing S may be a space between adjacent turns of the wire, and a turn width is denoted as W. A ratio of W/S may be not larger than 10.

Abstract: The invention relates to systems and methods for charging a vehicle. A vehicle and charging station can be designed such that an electric or hybrid vehicle can operate in a fashion similar to a conventional vehicle by being opportunity charged throughout a known route.

Abstract: Method for automatically analyzing complex electronic circuit designs for generalized types of floating FET gate circuit design errors that encompass both standard floating gate issues and previously difficult-to-find high impedance situations. The invention views electronic circuits as comprising a large number of “circuit stacks”, each stack having a small number of electronic devices between a given power and ground rail within the circuit. The invention uses a computer processor and a recursion algorithm to automatically analyze circuit netlists, determine the different circuit stacks, stack input-output functions, and stack devices, and use an expression algorithm to determine a logical expression of the given stack's input-output function.

Abstract: A transmission gate structure includes first and second PMOS transistors in a first active area and first and second NMOS transistors in a second active area. The first and second PMOS transistors include first and second gate structure, the first NMOS transistor includes a third gate structure coupled to the second gate structure, and the second NMOS transistor includes a fourth gate structure coupled to the first gate structure. A first metal zero segment overlies the first active area, a second metal zero segment is offset from the first metal zero segment by an offset distance, a third metal zero segment is offset from the second metal zero segment by the offset distance, and a fourth metal zero segment is offset from the third metal zero segment by the offset distance and overlies the second active area.

Abstract: A method includes generating gate-level activity information of a processor design for all possible executions of a target application for any possible inputs to the target application. The method includes performing a constrained timing analysis on the processor design based on the gate-level activity information to determine a minimum operating voltage for executing the target application on the processor.

Abstract: A method for calculating cell edge leakage in a semiconductor device comprising performing a device leakage simulation to obtain leakage information for different cell edge conditions and providing attributes associated with cell edges in the semiconductor device. The method further comprises performing an analysis to identify cell abutment cases present in the semiconductor device and calculating the leakage of the semiconductor device based at least in part on probabilities associated with the cell abutment cases and the simulated leakage values obtained from the device leakage simulation.

Abstract: An electromigration (EM) sign-off methodology that analyzes an integrated circuit design layout to identify heat sensitive structures, self-heating effects, heat generating structures, and heat dissipating structures. The EM sign-off methodology includes adjustments of an evaluation temperature for a heat sensitive structure by calculating the effects of self-heating within the temperature sensitive structure as well as additional heating and/or cooling as a function of thermal coupling to surrounding heat generating structures and/or heat sink elements located within a defined thermal coupling range.

Abstract: Automated routing of signal nets for interposer designs. Signal nets are defined by their endpoints (bumps). The nets and their corresponding bumps are assigned to bump groups, based on the relative locations of the bumps and also based on length-matching constraints for the nets. Some of the bump groups may be “clones,” where the routing for one bump group may also be applied to its clone. In order for two bump groups to be clones, the bumps in the two bump groups must have a same relative position (i.e., same bump pattern), and the nets in the two bump groups must be subject to the same length-matching constraint. The routing through the interposer for one of the clones is determined, and that routing is then replicated for the other clones.

Abstract: Exploiting FPGAs for acceleration may be performed by transforming concurrent programs. One example mode of operation may provide one or more of creating synchronous hardware accelerators from concurrent asynchronous programs at software level, by obtaining input as software instructions describing concurrent behavior via a model of communicating sequential processes (CSP) of message exchange between concurrent processes performed via channels, mapping, on a computing device, each of the concurrent processes to synchronous dataflow primitives, comprising at least one of join, fork, merge, steer, variable, and arbiter, producing a clocked digital logic description for upload to one or more field programmable gate array (FPGA) devices, performing primitive remapping of the output design for throughput, clock rate and resource usage via retiming, and creating an annotated graph of the input software description for debugging of concurrent code for the field FPGA devices.