Abstract: An electromigration (EM) sign-off methodology that analyzes an integrated circuit design layout to identify heat sensitive structures, self-heating effects, heat generating structures, and heat dissipating structures. The EM sign-off methodology includes adjustments of an evaluation temperature for a heat sensitive structure by calculating the effects of self-heating within the temperature sensitive structure as well as additional heating and/or cooling as a function of thermal coupling to surrounding heat generating structures and/or heat sink elements located within a defined thermal coupling range.

Abstract: Automated routing of signal nets for interposer designs. Signal nets are defined by their endpoints (bumps). The nets and their corresponding bumps are assigned to bump groups, based on the relative locations of the bumps and also based on length-matching constraints for the nets. Some of the bump groups may be “clones,” where the routing for one bump group may also be applied to its clone. In order for two bump groups to be clones, the bumps in the two bump groups must have a same relative position (i.e., same bump pattern), and the nets in the two bump groups must be subject to the same length-matching constraint. The routing through the interposer for one of the clones is determined, and that routing is then replicated for the other clones.

Abstract: Exploiting FPGAs for acceleration may be performed by transforming concurrent programs. One example mode of operation may provide one or more of creating synchronous hardware accelerators from concurrent asynchronous programs at software level, by obtaining input as software instructions describing concurrent behavior via a model of communicating sequential processes (CSP) of message exchange between concurrent processes performed via channels, mapping, on a computing device, each of the concurrent processes to synchronous dataflow primitives, comprising at least one of join, fork, merge, steer, variable, and arbiter, producing a clocked digital logic description for upload to one or more field programmable gate array (FPGA) devices, performing primitive remapping of the output design for throughput, clock rate and resource usage via retiming, and creating an annotated graph of the input software description for debugging of concurrent code for the field FPGA devices.

Abstract: In some embodiments, a client device may obtain an external signal. The hardware components of an integrated circuit of the client device may be reconfigured from a first configuration to a second configuration based on information in the external signal such that one or more portions of the integrated circuit that was previously inaccessible is now accessible and an application may access the one or more portions of the integrated circuit. Further, in response to a trigger, the components of the integrated circuit may reconfigure from the second configuration to the first configuration such that the one or more portions of the integrated circuit is inaccessible.

Abstract: Systems and methods of developing an integrated circuit implement selecting a desired yield for a circuit used in the integrated circuit. The desired yield corresponds to a desired failure probability of the circuit. The method includes determining a parameter threshold value that corresponds with the desired yield. The circuit passes if a parameter associated with the circuit is below the parameter threshold value and the desired yield indicates a percentage of instances of the circuit that pass according to the parameter threshold value. The method also includes using the parameter threshold value that corresponds with the desired yield during testing and improvement of a design of the integrated circuit, and providing the design of the integrated circuit for fabrication.

Abstract: An automated method of determining power sequencing risks (e.g. power-up, power-down time sequences) for complex computer circuits with multiple independent power supplies. The method operates by logical consideration of the topological arrangement of MOSFETs and other devices in standard netlists. The invention inspects the various devices and automatically traces DC circuit paths to DC power rails. The invention then evaluates, as a type of logical existence proof, and on a per MOSFET device level, if due to assignment to different DC power levels, various factors, such as forward-biased diodes, floating MOSFET gate, and other risk factors could ever occur. The method generates comprehensive records of such risks and can output an overall analysis of a circuit reporting on both problematic power sequences, as well as circuit design factors that may be sub-optimal from a power sequence perspective.

Abstract: An optical proximity correction (OPC) method may include providing a design layout including conductive patterns, determining line end void (LEV)-risk patterns among the conductive patterns, the LEV-risk patterns each having a risk of suffering from poor contact due to an LEV, setting markers including portions of the LEV-risk patterns and portions of the conductive patterns adjacent to the LEV-risk patterns, performing a first OPC on first patterns included in the markers and performing a second OPC on second patterns outside the markers, the second OPC being different from the first OPC, and each of the first OPC and the second OPC being performed a plurality of times, and calculating a cost function of each of the markers. The determining may include comparing risks of occurrence of poor contact in each of the conductive patterns based on a scoring function, and the scoring function may be inversely proportional to a width of each of the conductive patterns.

Abstract: According to one embodiment, a mask pattern correction system includes the following configuration. A stress analysis circuitry divides a layout of a circuit pattern formed using a design mask formed in accordance with mask design data into correction regions, and acquires a displacement amount from the regions. A correction value calculation circuitry calculates a displacement correction value from the displacement amount. A correction map generation circuitry generates a correction map based on a correction value difference of the displacement correction values. A mask position correction circuitry allocates the regions to a layout of the circuit pattern, performs displacement correction of a mask pattern on the design mask by the displacement correction values, and creates a correction mask based on the displacement correction.

Abstract: A method of generating a netlist of an IC device includes extracting dimensions of a gate region of the IC device, the dimensions including a width of the gate region, the width extending at least from a first edge of an active region to a second edge of the active region, and a distance from a first end of the width to a gate via positioned along the width. A first gate resistance value corresponding to the gate region is received, a second gate resistance value is determined based on the distance and the width, and the netlist is updated based on the first and second gate resistance values.

Abstract: Systems and methods for applying spatial correlation in integrated circuit development involve placing devices of an integrated circuit design, and obtaining spatial correlation values. Each spatial correlation value indicates a correlation coefficient between a first device and a second device, which are instances of a same device. The correlation coefficient is based on a device separation. Spatial correlation is determined as a function of an inverse of device separation. The device separation refers to one-dimensional or two-dimensional separation. The method includes determining a parameter value for the first device based on an average value of the parameter value and on the spatial correlation as the function of the inverse of the device separation, performing analysis of the integrated circuit design using the parameter value, and providing the integrated circuit design for fabrication into an integrated circuit based on finalizing the design according to the analysis.

Abstract: A method a system include obtaining a master list of layer traits including wire codes, each of the wire codes indicating a width of a corresponding wire, and including a maximum reach length of the corresponding wire and a time of flight (TOF) through the corresponding wire. The method also includes processing the master list of the layer traits to obtain a final list of the layer traits, the final list of the layer traits having fewer entries than the master list of the layer traits and being in a ranked order. A metric is calculated for each adjacent pair of the layer traits in the final list of layer traits. The final list of the layer traits and the corresponding metric is used to assign the corresponding wires to different interconnects among components of an integrated circuit.

Abstract: A method for predicting local layout effect in a circuit design pattern includes obtaining a plurality of circuit design patterns, generating layout images from the circuit design patterns, extracting feature vectors from the layout images by processing the layout images in a computer vision machine learning algorithm, comparing the feature vector extracted from a selected layout image to clusters of feature vectors extracted from the layout images, wherein the clusters of feature vectors include an in-range cluster and an outlier cluster, and labelling a circuit design pattern corresponding to the selected layout image, for which threshold voltage has not been experimentally measured, as being an in-range circuit design pattern or an outlier circuit design pattern, in response to the selected layout image respectively correlating with the in-range cluster or with the outlier cluster.

Abstract: An electronic device is disclosed. The disclosed electronic device includes a display, a charging circuit that transmits and receives power to and from an external electronic device, a sensor circuit that senses a spatial relationship of the electronic device with the external electronic device, a processor that is electrically connected with the display, the charging circuit, and the sensor circuit. When wirelessly transmitting or receiving power to or from the external electronic device using the charging circuit, the processor may transmit and receive information associated with the wireless transmission or reception of power and display the information based on the spatial relationship.

Abstract: A timing model building method, for building a timing model corresponding to a gate-level netlist of a block, includes the following operations: utilizing a processor to generate an interface net of the gate-level netlist, where if the gate-level netlist comprises an unconstrained clock tree and boundary timing constraint information of the gate-level netlist does not comprise a timing constraint of the unconstrained clock tree, the interface net comprises none of cells of the gate-level netlist driven by the unconstrained clock tree; utilizing the processor to generate an identified internal net of the gate-level netlist, where the identified internal net is cross-coupled to the interface net; and utilizing the processor to generate the timing model according to the interface net and the identified internal net.

Abstract: A power converter comprises a high side switching element and a low side switching element arranged in series between an input terminal of the power converter and a reference terminal. A first feedback circuit of the power converter is configured to control an output voltage or an output current at an output terminal of the power converter. The first feedback circuit comprises a first comparator configured to generate a first control signal for controlling the switching of the switching elements by comparing a first error voltage with a first ramp signal. A second feedback circuit of the power converter is also configured to control said output voltage or said output current. The second feedback circuit comprises a second comparator configured to generate a second control signal by comparing a second error voltage with a second ramp signal.

Abstract: Examples herein describe techniques for optimizing a hardware design for an integrated circuit. Instead of trying multiple optimization strategies each time design code is synthesized, the embodiments herein describe identifying the optimal or best optimization strategy for a particular combinational module in the design code only one time. Then, each time the design code is synthesized in the future, a synthesis tool recognizes the combinational module and selects the best optimization strategy. To do so, the synthesis tool generates a signature using the circuit structure represented by a netlist. The synthesis tool traverses the netlist and assigns unique integers to the primary inputs, the combination instances, and the primary outputs. These integers can then be fed into a signature generator which outputs a signature for the combinational module.

Abstract: A design system accesses at least one placement template for at least one structured soft block composed of a pre-defined set of cells with relative placement information for the pre-defined set of cells. The design system optimizes implementation of the at least one structured soft block by propagating constants while preserving relative placement structure of the pre-defined set of cells within each at least one structured soft block according to the respective at least one placement template accessed for the at least one structured soft block.

Abstract: Systems, methods, media, and other such embodiments described herein relate to critical area analysis (CAA) operations as part of electronic design automation (EDA). One embodiment involves accessing a circuit design having a first layer (which may be a composite layer), sampling the first layer, and performing an initial CAA using the sampled portions of the layer with a set of predetermined defect sizes. The initial CAA is used to automatically generate a model which can be used to accurately select input parameters (e.g., selected defect sizes) for a full analysis. A CAA characteristic is then calculated for the first layer using the input parameters. In various embodiments, different sampling percentages and criteria for selecting input parameters can be used to reduce the computing resources to compute a CAA characteristic, such as theta-bar, while limiting error to a threshold amount (e.g. less than one percent).

Abstract: A rechargeable battery pack for a hand-held power tool, including a rechargeable battery pack housing, the rechargeable battery pack housing accommodating at least two rechargeable battery cells. The rechargeable battery pack is mechanically and electrically connectable to a hand-held power tool and/or to a charging device via an interface. The interface includes contact elements for electrically and/or mechanically contacting corresponding countercontact elements on the hand-held power tool and/or corresponding countercontact elements on the charging device. It is provided that the rechargeable battery pack housing includes at least one first rechargeable battery cell string for accommodating at least one first rechargeable battery cell, and at least one second rechargeable battery cell string for accommodating at least one second rechargeable battery cell. The rechargeable battery pack housing includes at least two electrical contact elements for each rechargeable battery cell string.

Abstract: The present embodiments are generally directed to electronic circuit design and verification and more particularly to techniques for characterizing electronic components within an electronic circuit design for use in verification. In one or more embodiments, an adaptive sensitivity based analysis is used to build an adaptive equation to represent the timing response surface for an electronic component. With the adaptive surface response built, a sample-based evaluation yields highly accurate extraction of electronic component timing parameters including on-chip variation information such as sigma and moments.