Abstract: A method, computer program product, and a fail recognition apparatus are disclosed for debugging one or more simulation fails in processor design verification that in one or more embodiments includes determining whether a prediction model exists; retrieving, in response to determining the prediction model exists, the prediction model; predicting one or more bug labels using the prediction model; determining whether a fix is available for the one or more predicted bug labels; and simulating, in response to determining the fix is available for the one or more predicted bug labels, the fix for the one or more predicted bug labels.

Abstract: Disclosed is an approach for implementing placement for an electronic design, where when a dragged object is moved into a desired area, existing objects in that location are automatically moved as necessary in correspondence to the movement of the dragged object. Existing objects are only moved if they are causing a spacing violation or overlap with the dragged object being moved, either directly or indirectly.

Abstract: A method includes designing a first layout of gate structures and diffusion regions of a plurality of active devices, identifying an edge device of the plurality of active devices, modifying the first layout resulting in a second layout, performing a design rule check on the second layout, and fabricating, based on the second layout, at least one of a photolithography mask or at least one component in a layer of a semiconductor device. Modifying the first layout includes adding a dummy device next to the edge device, adding a dummy gate structure next to the dummy device and extending a shared diffusion region to at least the dummy device. The dummy device and the edge device have the shared diffusion region. Performing the design rule check considers a gate structure of the dummy device as one of two dummy gate structures next to the edge device.

Abstract: Using a high-level language (HLL) callable library for multiple instances of a core includes detecting, using computer hardware, a reference to an HLL library for a core within an HLL application, determining, using the computer hardware, a plurality of instances of the core by detecting function calls within the HLL application correlated to each of the plurality of instances of the core, and generating, using the computer hardware, interface code within the HLL application for each of the plurality of instances of the core using the HLL library. An executable version of the HLL application is generated, using the computer hardware, wherein the interface code for each of the plurality of instances of the core is bound to the respective instance of the core. The function calls can specify different parameterization files corresponding to the plurality of instances of the core.

Abstract: Creating a high-level language (HLL) callable library for a hardware core can include automatically querying, using computer hardware, a metadata description of a core to determine a plurality of available ports of the core, automatically determining, using the computer hardware, an argument of a first function specified in a header file corresponding to the core, mapping, using the computer hardware, the argument to a first port of the plurality of available ports, and automatically generating and storing, using the computer hardware, an HLL library specifying a mapping of the argument to the first port of the core. The HLL library is configured for inclusion with a user application during compilation.

Abstract: A method for manufacturing an integrated circuit includes determining a static probability pattern of a circuit cell in a timing path of the integrated circuit; determining a timing delay of the circuit cell along the timing path according to the static probability pattern and a pattern based timing database, wherein the pattern based timing database indicates a plurality of reference delays of each timing arc of the circuit cell characterized in response to a plurality of input stress patterns respectively; and manufacturing the integrated circuit according to the timing delay of the circuit cell along the timing path.

Abstract: A power tool system includes a hand-held power tool having a power tool housing accommodating a motor, and a battery pack interface electrically connected to the motor within the power tool housing. A battery pack includes a battery pack housing accommodating at least one battery cell and a power tool interface electrically connected to the at least one battery cell within the battery pack housing. The power tool interface is configured to be physically and electrically connected to and disconnected from the battery pack interface of the power tool. A communicator is attached to or accommodated within the battery pack housing. The communicator is configured to wirelessly communicate with an external device.

Abstract: Provided is a semiconductor LSI design device that includes: a unit that generates a combinational circuit constituted by combining function blocks defined by a function block library from an application specification, by assigning connection information on an operation order of the function blocks; a unit that converts the combinational circuit to operation order information that is applicable to a sequential circuit in which a function block is used a plurality of times in a time-division manner; a unit that inversely converts the generated operation order information to a combinational circuit; a unit that verifies logical equivalence of the combinational circuit and the inversely converted combinational circuit; and a unit that combines the operation order information, the sequential circuit and a function block.

Abstract: A battery control apparatus is applied to a power supply system that includes a storage battery including a plurality of battery cells, an electrical apparatus connected to the storage battery, and a cell monitoring apparatus connected to each battery cell of the storage battery. In the battery control apparatus, a total cell voltage calculating unit calculates a sum of the voltages of battery cells detected by a cell monitoring apparatus as a total cell voltage. A voltage acquiring unit acquires a voltage of the cell monitoring apparatus side of a resistor that is provided on a conduction path. A consumed current calculating unit calculates a consumed current that is consumed by the cell monitoring apparatus based on the total cell voltage and the voltage acquired by the voltage acquiring unit. A residual capacity calculating unit calculates the residual capacity based on the charge-discharge current and the consumed current.

Abstract: Aspects of the disclosed technology relate to techniques for achieving optical proximity correction cross-tile consistency. A layout design is divided into a plurality of regions. Optical proximity correction iterations are performed on each of the plurality of regions to generate a modified layout design. Based on the modified layout design and the layout pattern surrounding each of the edge fragments in the modified layout design, a final modified layout design is generated such that the edge fragments in different regions in the plurality of regions in the final modified layout design having the same layout pattern have a same edge adjustment value with respect to the layout design.

Abstract: Systems and methods are provided for identifying a wire of a plurality of wires to be adjusted to mitigate effects of electromigration. A segment electromigration stress value for each segment of a wire is determined for a wire of a circuit in a circuit design. A wire electromigration stress value for the wire is determined as a function of the segment electromigration stress values of segments of the wire. A ranked list of two or more wires of the circuit is displayed according the wire electromigration stress values of the two or more wires.

Abstract: A current detecting apparatus and a battery management system are provided. In the current detecting apparatus, a positive electrode of a power battery pack is connected to a first terminal of a primary positive circuit, a negative electrode of the power battery pack is connected to a first terminal of a primary negative circuit, and a current sensor is connected in series between the negative electrode of the power battery pack and the first terminal of the primary negative circuit; the current sensor is configured for obtaining and outputting a voltage signal of the power battery pack; a microcontroller unit is configured for implementing current conversion on the voltage signal, transmitting a detected current value, which is obtained by the current conversion, of the power battery pack and receiving a control command for controlling the primary positive and negative circuits to turn on or turn off.

Abstract: A layout modification method for fabricating a semiconductor device is provided. Uniformity of critical dimensions of a first portion and a second portion in a patterned layer is calculated by using a layout for an exposure manufacturing process to produce the semiconductor device. The second portion is adjacent to the first portion, and a width of the second portion equals a penumbra size of the exposure manufacturing process. The penumbra size is utilized to indicate which area of the patterned layer is affected by light leakage exposure from another exposure manufacturing process. Non-uniformity between the first and second portions of the patterned layer is compensated according to the uniformity of critical dimensions to generate a modified layout.

Abstract: The independent claims of this patent signify a concise description of embodiments. Each component of a testbench configured to test a DUT is associated at compile time with a different hardware transactor. The testbench is partitioned at compile time into a plurality of independent partitioned testbenches, where each independent partitioned testbench comprises at least one component of the testbench. At run time, each of the plurality of partitioned testbenches is simulated in parallel. The simulating of a partitioned testbench includes execution of its at least one component on its at least one associated hardware transactor using the hardware emulation system. This Abstract is not intended to limit the scope of the claims.

Abstract: The present disclosure, in some embodiments, relates to an electromigration sign-off tool. The tool includes electronic memory configured to store an integrated chip design and an environmental temperature having a same value corresponding to a plurality of interconnect wires within the integrated chip design. An adder is configured to add the environmental temperature to a plurality of real temperatures to determine a plurality of actual temperatures having different values corresponding to different ones of the plurality of interconnect wires. The plurality of real temperatures account for Joule heating on the plurality of interconnect wires. An average current limit calculation element is configured to determine an average current limit at a first one of the plurality of actual temperatures. A comparator is configured to determine an electromigration violation on a first interconnect wire by comparing the average current limit to an average current of the first interconnect wire.

Abstract: A charge control circuit includes: a charge current control circuit configured to receive an input voltage at a first node, output a sensing current to a second node, and turn on a power transistor; a comparator configured to compare a voltage level of the second node with a voltage level of a third node, wherein the third node receives a charging current from the power transistor; a current mirror configured to generate a mirror current corresponding to the sensing current; and an amplifier configured to receive a first feedback voltage based on the mirror current, and amplify a difference between the first feedback voltage and a reference voltage to generate a switch control signal, wherein in response to the switch control signal and a plurality of control signals, the charge current control circuit is configured to decrease the sensing current and turn on the power transistor.

Abstract: A vehicle power supply device that includes a control unit that performs at least a quick charging control which causes the first voltage converter to perform the charging operation and causes the second voltage converter to perform the charging operation, and a charging/discharging control which causes the first voltage converter to perform the charging operation and causes the second voltage converter to perform the discharging operation.

Abstract: A system and method for wirelessly authorizing access to a charge port for an electric vehicle is provided. The system may first establish a wireless communication link with a charging cord and then receive, from the charging cord, a wireless signal including a charging cord identifier. Upon verifying that the charging cord is authorized for use with the electric vehicle based on the charging cord identifier, a charge port door may be opened providing access to the charge port. A wireless communication link with a charging cord may be established using a challenge-response protocol like some passive entry systems. Alternatively, a wireless communication link may be established using radio-frequency identification (RFID) technology embedded in the charge port and the charging cord handle.

Abstract: Disclosed are method(s), system(s), and article(s) of manufacture for implementing layouts for an electronic design using machine learning, where users re-use patterns of layouts that have been previously implemented, and those previous patterns are applied to create recommendations in new situations. An improved approach to perform cross-validations is provided.

Abstract: Aspects of the disclosed technology relate to techniques of bandwidth test in networking system-on-chip design verification. A hardware model of interface circuitry implemented in a reconfigurable hardware modeling device associates dispatch time information with messages when the messages are dispatched by a hardware model of a circuit design implemented in the reconfigurable hardware modeling device. The dispatch time information of a particular message includes information about when, based on a model time reference provided in the reconfigurable hardware modeling device, the particular message is dispatched by the hardware model of the circuit design. The messages and the dispatch time information are sent to a traffic analysis device, which determines bandwidth information of ports of the circuit design based on the dispatch time information.