Abstract: The present embodiments relate to reconfiguration of a schematic. According to some aspects, embodiments relate to a method in which a schematic of a circuit is displayed on a graphical user interface of a computing device. The schematic can include a plurality of circuit objects, and at least one interconnect connecting the plurality of circuit objects to define a circuit connectivity. The method further includes defining a schematic reference point on the schematic. The method also includes determining a distance of each circuit object of the plurality of circuit objects from the schematic reference point. The method also includes increasing the distance of each circuit object of the plurality of circuit objects from the schematic reference point relative to a respective size of each circuit object, wherein increasing the distance includes multiplying the distance by a scaling factor. The at least one interconnect is reconfigured to maintain circuit connectivity.

Abstract: Provided is a technology that can improve a cycle property without lowering a volume energy density. The present technology provides a method for evaluating a secondary battery, including conducting at least: a determination step of determining a degree of diffusion defect of an ion that performs electric conduction; an evaluation step of evaluating a state of the secondary battery on the basis the result of the determination in the determination step; and a control step of controlling states of current application and voltage application on the secondary battery during charging or during discharging of the secondary battery on the basis of the result of the evaluation in the evaluation step.

Abstract: The present disclosure relates to a system and method for mapping an RTL vector file to an electronic design. Embodiments may include receiving, at one or more computing devices, an electronic design at an electronic design automation application and reading at least one gate-level netlist associated with the electronic design. Embodiments may also include preparing each gate object with different transformations so to match a register-transfer-level name and reading at least one vector object from one or more register-transfer-level vector files. Embodiments may further include attempting to identify at least one match in the gate-level netlist, wherein the at least one match is a match between a register-transfer-level name and a gate name. Embodiments may also include writing a validation file including at least one of mapped information and unmapped information.

Abstract: A computer implemented method of translation of verification commands of an electronic design, comprises the steps of receiving the electronic design, receiving at least one analog test harness model having at least one indirect branch contribution statement and having at least one of at least one stimulus parameter stored in at least one specification database and at least one measurement parameter stored in at least one specification database and at least one specification parameter stored in at least one specification database, translating the at least one indirect branch contribution statement into a plurality of direct branch contribution operators based at least in part upon the at least one analog test harness model and at least one of at least one stimulus parameter stored in at least one specification database and at least one measurement parameter stored in at least one specification database and at least one specification parameter stored in at least one specification database and generating a netl

Abstract: A method for recharging a battery pack (40; 40?) includes attaching a portable charger (120) to a user, which portable charger comprises or is attached to a self-contained power supply (130, 140) and wherein a first charging port (132, 146) of the portable charger is disposed, e.g., on a belt (144) worn by the user, hanging the battery pack on the belt while the battery pack is physically engaged and in electrical communication with a power tool (10; 10?), and initiating a transfer of power from the charger to the battery pack when the first charging port is at least proximal to a second charging port (85, 148) that is in electrical communication with at least one battery cell (50) of the battery pack. A portable charging system capable of performing this method, as well as an adapter for use in performing this method, are also disclosed.

Abstract: The present inventions, in one aspect, are directed to techniques and/or circuitry to applying a charge pulse to the terminals of the battery during a charging operation, measure a plurality of voltages of the battery which are in response to the first charge pulse, determine a charge pulse voltage (CPV) of the battery, wherein the charge pulse voltage is a peak voltage which is in response to the first charge pulse, determine whether the CPV of the battery is within a predetermined range or greater than a predetermined upper limit value and adapt one or more characteristics of a charge packet if the CPV is outside the predetermined range or is greater than a predetermined upper limit value.

Abstract: An integrated circuit includes a plurality of vertically-stacked layers including a front end of line (FEOL) layer and a back end of line (BEOL) layer. The FEOL layer includes individual transistors that are not interconnected. The BEOL layer includes transistor interconnections and no transistors. The transistors are electrically connected to the transistor interconnections by vias within the FEOL ad BEOL layers. The FEOL and BEOL layers each have contact pads on the top and bottom surfaces thereof that are each in alignment with vias, are arranged in a checkerboard pattern, and occupy about fifty percent of the surface area of the FEOL and BEOL layers. The contact pads on a top surface of the FEOL layer are in electrical communication with contact pads on a bottom surface of the BEOL layer to facilitate vertical current flow between the transistors and the transistor interconnections through the vias.

Abstract: The present disclosure relates to a computer-implemented method for simulating a circuit design having a discrete domain segment connected to a continuous domain segment at a connection point. The method may include inserting a bidirectional interface element at the connection point located between the discrete domain segment and the continuous domain segment. The method may also include splitting the discrete domain segment into a plurality of transistor network models to provide for bi-directional transfer of data between the continuous domain segment and the discrete domain segment, wherein at least one of the plurality of transistor network models utilizes only one or more drivers external to a module.

Abstract: A hardware verification system includes, in part, a multitude of programmable devices and a system clock. The hardware verification system receives a circuit design and generates a variable period clock from the system clock by analyzing propagation delays in different signal paths of the circuit design. The variable period clock has a first period that occurs in each N cycles of the system clock and a second period that occurs in each M cycles of the system clock, in which M>N. The variable period clock is applied to at least one of the programmable devices to verify the circuit design.

Abstract: In one embodiment, a method for performing an analysis of a synthesized clock tree can include: displaying a plurality of variation parameters and one or more analysis values on a display screen; accepting a first signal from a user input device to select one of the variation parameters; accepting a second signal from a user input device to select one or more of the analysis values; and displaying a plurality of pins from the synthesized clock tree with the selected variation parameter and the selected one or more analysis values on the display screen.

Abstract: A method is presented for responding to user input by displaying when a circuit has a property expressed by an assertion based on data indicating values of signals of the circuit at a succession of times. The assertion expresses the property as a first sequence of expressions, and separately defines for each expression a corresponding evaluation time relative to the succession of times at which the expression is to be evaluated. The circuit has the property only if every expression of the first sequence evaluates true at its corresponding evaluation time. The method includes displaying a representation of each expression of the first sequence and identifying each variable that caused that expression to evaluate false and distinctively marking that variable's symbol relative to other variable symbols within the display for each expression of the first sequence that evaluates false at its corresponding evaluation time.

Abstract: A layout modification method for fabricating an integrated circuit is provided. The layout modification method includes calculating uniformity of critical dimension of a patterned layer with a layout for an exposure manufacturing process to produce a semiconductor device. The patterned layer is divided into a first portion and a second portion which is adjacent to the first portion, and a width of the second portion equals to a penumbra size of the exposure manufacturing process. The layout modification method further includes retrieving an adjusting parameter for modifying the layout of the semiconductor device; determining a compensation amount based on the adjusting parameter and the uniformity of critical dimension; and compensating the critical dimension of the second portion of the patterned layer by utilizing the compensation amount to generate a modified layout.

Abstract: Aspects of the disclosure are directed to a metal only cell-based power grid (PG) architecture. In accordance with one aspect, the power gird (PG) architecture includes a cell building block structure with a N×M grid configuration including N cell building blocks arranged in a first direction and M cell building blocks arranged in a second direction, wherein the first direction and the second direction are orthogonal to one another; and a plurality of power grid (PG) cells, wherein each of the N cell building blocks and each of the M cell building blocks are occupied by a PG cell of the plurality of PG cells.

Abstract: Methods, systems, and computer-readable storage media for receiving data representative of the temporal graph, the data representing vertices, edges between vertices, and temporal features, determining a set of earliest-arrival dependencies, each earliest arrival dependency including an earliest feasible edge between vertices from a list of edges of the temporal graph, providing data representative of an edge-scan-dependency graph (ESD-graph) based on the data representative of the temporal graph, and the set of earliest-arrival dependencies, the ESD-graph including vertices representing edges of the temporal graph, and edges representing earliest-arrival dependencies between vertices, providing data representative of a level-assigned ESD-graph including a level assigned to each vertex of the ESD-graph, and determining earliest-arrival times between a source vertex, and each vertex of the temporal graph by executing a parallel edge scan of the level-assigned ESD-graph.

Abstract: A method for visually merging design databases without generating a merged database of the design databases is disclosed. A first display window that is to display information from a particular database in non-overlay mode is assigned to the first stack position, and a second display window that is to display information from another database in overlay mode is assigned to a next stack position. The second display window is positioned relative to the first display window using position information received from the first display window via an inter-process communication channel.

Abstract: The present disclosure, in some embodiments, relates to a method of performing electromigration sign-off. The method includes determining an environmental temperature having a same value corresponding to a plurality of interconnect wires within a plurality of electrical networks of an integrated chip design. A plurality of actual temperatures having different values corresponding to different ones of the plurality of interconnect wires are determined. The plurality of actual temperatures are respectively determined by adding the environmental temperature to a real temperature that accounts for Joule heating one of the plurality of interconnect wires. An electromigration margin for a first interconnect wire within a first electrical network of the plurality of electrical networks is determined. The electromigration margin is determined at a first one of the plurality of actual temperatures corresponding to the first interconnect wire. The electromigration margin is compared to an electromigration metric.

Abstract: A battery pack includes a plurality of rechargeable batteries, a sensor, and a battery manager. The sensor obtains motion information of the rechargeable batteries. The motion information includes at least one of first information obtained by sensing whether the rechargeable batteries are in a movement state or in a standstill state or second information on a state in which the rechargeable batteries are inclined. The second information may be obtained based on a change in angle when the rechargeable batteries are in the movement state. The battery manager control charging or discharging of the rechargeable batteries in a charge mode or a discharge mode based on the motion information.

Abstract: A method includes designing a layout of gate structures and diffusion regions of a plurality of devices, identifying an edge device of the plurality of devices, adding a dummy device next to the edge device and a dummy gate structure next to the dummy device resulting in a modified layout, and fabricating, based on the modified layout, at least one of a photolithography mask or at least one component in a layer of a semiconductor device. The dummy device shares a diffusion region with the edge device. A gate structure of the dummy device is one of two dummy gate structures added next to the edge device.

Abstract: A computer implemented method of passive verification of an electronic design, comprising receiving an electronic design file of said electronic design comprised at least in part of a mixed signal or analog system including a plurality of subsystems. At least one analog subsystem of the plurality of subsystems has at least two design representations within the electronic design file that are intended to be equivalent for the at least one analog subsystem being simulated. First and second input subsystem data is collected for a first and second subsystem design representation of the at least two design representations from an analog stimulus to at least one input of the first and second subsystem design representation which is analog.

Abstract: The invention relates to a method for the voltage-controlled deactivation of battery cells (22) within a battery module (34, 38) or a battery pack (48) and for the voltage-controlled deactivation of electronic components (40, 52.1-52.8, 54) which are electrically connected to the battery cells and which are supplied with power by the battery cells. If a voltage falls below a threshold in the battery cells (22), supply lines (44, 46, 68, 70) to the electronic components (40, 52.1-52.8, 54) are automatically interrupted and/or battery cells (22) of the battery modules (34, 38) are separated from the main current circuit of the battery or of a battery pack (48).