Abstract: Disclosed herein are embodiments of systems, methods, and products to automatically and intelligently generate a test bench to test an electrostatic discharge (ESD) protection circuit in an integrated circuit (IC) design. A computer may receive netlist of the IC design forming a device under test (DUT). From the DUT, the computer may extract and/or calculate one or more parameters. Based on the one or more parameters, the computer may generate a test bench comprising a resistance inductance capacitance (RLC) circuit to provide ESD stimulus to the DUT. The ESD stimulus and therefore the test bench may be based on a human body model (HBD) or a charged device model (CDM). In case of the CDM, the computer may allow a circuit designer to select or deselect package parameters for testing the ESD protection circuit.

Abstract: Embodiments described herein provide a method shifting mask pattern data during a digital lithography process to reduce line waviness of an exposed pattern. The method includes providing a mask pattern data having a plurality of exposure polygons to a processing unit of a digital lithography system. The processing unit has a plurality of image projection systems that receive the mask pattern data. Each image projection system corresponds to a portion of a plurality of portions of a substrate and receives an exposure polygon corresponding to the portion. The substrate is scanned under the plurality of image projection systems and pluralities of shots are projected to the plurality of portions while shifting the mask pattern data. Each shot of the pluralities of shots is inside the exposure polygon corresponding to the portion.

Abstract: Embodiments of the invention are directed to methods, systems, and computer program products for the hierarchical management of self-aligned double patterning (SADP) trim shapes. Non-limiting embodiments of the invention include receiving, by a processor, one or more virtual trim shapes at a boundary between a parent hierarchy block and a child hierarchy block. The trim shapes are aligned to a legal trim grid. The processor then places one or more trim shapes aligned with the legal trim grid.

Abstract: The invention relates to an integrated circuit comprising: a row of sink cells, a first driver cell, a second driver cell, an interconnect line connecting the first driver cell to the sink cells of the row; and a shunt line connecting the second driver cell to a point between ends of the interconnect line, wherein a segment of the interconnect line between the point and the first driver cell is bigger than 60% of a length the interconnect line and less than 80% of the length of the interconnect line.

Abstract: Program procedures executed to rout a bus, via a processing unit, include a bus information extractor configured to extract bus information including physical requirements for the bus, from input data, a buffer array generator configured to generate a buffer array in which buffers included in the bus are regularly arranged based on the bus information, a buffer array placer configured to place at least one buffer array in the layout of the integrated circuit based on the bus information, and a wiring procedure configured to generate interconnections connected to buffers included in the at least one buffer array based on the bus information.

Abstract: An electronic device is provided. The electronic device includes a housing, a battery included within the housing, a connector electrically connected to an external power supply device including an integrated circuit (IC) and exposed to a part of the housing, and a power management unit included within the housing and electrically connected to the connector, wherein the power management unit is configured to communicate with the IC of the external power supply device, and wherein the connector is configured to receive a first current of a first current value during at least a part of the communication and to receive a second current of a second current value greater than the first current value during at least a part in which the communication is not performed.

Abstract: A thermal transient response simulation is performed for a structure having a plurality of thermal model elements. The thermal transient response simulation determines a relation between transient thermal impedance of the structure and time and a relation between maximum temperature change of each of the thermal model elements and time. An onset time at which energy reaches each of the thermal model elements is determined based on the relation between maximum temperature change of each of the thermal model elements and time and a predetermined maximum temperature change threshold. An influence onset resistance value for each of the thermal model elements is determined by looking up a thermal resistance value corresponding to the onset time based on the relation between transient thermal impedance of the structure and time. A structural function is mapped based on the influence onset resistance value for each of the thermal model elements.

Abstract: Embodiments of the present invention provides methods, computer program products, and a system for processing hierarchical references for a formal equivalence check. In certain embodiments, hierarchical references of a first design are identified as functionally equivalent to hierarchical references of a second design. Value outputs of the first design can be compared to the value outputs of the second design to determine whether the value outputs of the respective designs match.

Abstract: A computer-implemented method, computer program product, and system for determination of critical parts and component correlations in a circuit using a correlation graph and centrality analysis including; receiving a circuit layout portion of a larger circuit layout, converting the circuit layout portion into a correlation graph representing components as nodes and connecting wires as edges, determining, using ground truth and Naïve Bayes to determine correlation weighting, scaling the correlation graph to represent the larger circuit, and presenting the larger correlation graph on a graphical user interface (GUI).

Abstract: Apparatuses and methods for removing a defective energy storage cell from an energy storage array is described. An apparatus includes an energy storage array including a plurality of energy storage cells, and a cell removal circuit coupled to the energy storage array. The cell removal circuit is configured to prevent a defective energy storage cell of the plurality of energy storage cells from causing other energy storage cells of the plurality of energy storage cells to become defective. A method includes receiving power at a charging node of an energy storage array, the energy storage array including a plurality of energy storage cells. Responsive to failure of an energy storage cell of the plurality of energy storage cells, current is provided through the defective energy storage cell, and responsive to the defective energy storage cell becoming an open circuit, discontinuing provision of the current through the defective energy storage cell.

Abstract: A two-way distribution, charging, and vending system permits a subscriber to exchange one or more partially or completely discharged portable electric energy storage devices for a comparable number of charged portable electric energy storage devices. The two-way distribution, charging, and vending system includes a number of charging modules, each with a dedicated power converter, communicably coupled to at least one two-way distribution system controller and to a power distribution grid. Upon receipt of a discharged portable electric energy storage device, the at least one two-way distribution system controller validates a manufacturer identifier and a subscriber identifier stored in a nontransitory storage media carried by the discharged portable electric energy storage device. Responsive to a successful authentication and validation, the at least one two-way distribution system controller dispenses a charged portable electric energy storage device to the subscriber.

Abstract: Methods for designing a processor based on executing a randomly created and randomly executed executable on a fabricated processor. By implementing randomization at multiple levels in the testing of the processor, coupled with highly specific test generation constraint rules, highly focused tests on a micro-architectural feature are implemented while at the same time applying a high degree of random permutation in the way it stresses that specific feature. This allows for the detection and diagnosis of errors and bugs in the processor that elude traditional testing methods. Once the errors and bugs are detected and diagnosed, the processor can then be redesigned to no longer produce the anomalies. By eliminating the errors and bugs in the processor, a processor with improved computational efficiency and reliability can be fabricated.

Abstract: Optical proximity correction (OPC) based computational lithography techniques are disclosed herein for enhancing lithography printability. An exemplary mask optimization method includes receiving an integrated circuit (IC) design layout having an IC pattern; generating target points for a contour corresponding with the IC pattern based on a target placement model, wherein the target placement model is selected based on a classification of the IC pattern; and performing an OPC on the IC pattern using the target points, thereby generating a modified IC design layout. The method can further include fabricating a mask based on the modified IC design layout. The OPC can select an OPC model based on the classification of the IC pattern. The OPC model can weight the target placement model.

Abstract: A method of manufacturing an image sensor that includes first and second semiconductor chips includes receiving manufacturing data respectively associated with the first and second semiconductor chips, processing the manufacturing data to determine a capacitance and a resistance of a pixel signal transmission line to which a pixel signal generated by each pixel of the plurality of pixels is transmitted, where the capacitance and the resistance corresponding to position information associated with each pixel of the plurality of pixels, and determining predicted characteristics of the image sensor based on the determined capacitance and resistance, prior to the first semiconductor chip being electrically connected to the second semiconductor chip. The first semiconductor chip may be electrically connected to the second semiconductor chip to form the image sensor based on a determination that the predicted characteristics of the image sensor at least meet a particular set of one or more target values.

Abstract: The invention relates to systems and methods for charging a vehicle. A vehicle and charging station can be designed such that an electric or hybrid vehicle can operate in a fashion similar to a conventional vehicle by being opportunity charged throughout a known route.

Abstract: An emulation process is performed with an emulator coupled to one or more targets. During a part or a whole of the emulation process, input signals to the emulator from the one or more targets are being captured, streamed out of the emulator and stored in one or more processor-readable media. The part or the whole of the emulation process is then repeated with the emulator decoupled to the one or more targets. During the repeating, the input signals stored in the one or more processor-readable media are being streamed back to the emulator. The streaming in both of the capture and replay modes may be through interfaces designed for small packets of data and fast streaming speed.

Abstract: Devices and methods are described relating to capacitor energy storage devices that are small in size and have a high energy stored to volume ratio. The capacitor devices include 2D material electrodes. The capacitor devices offer very fine granularity with high stacking possibilities which may be used in super capacitors and capacitor arrays. The devices include interleaved laminations 2D material electrode layers, for example graphene, and dielectric layers, for example Hafnium Oxide. In an embodiment a capacitor device includes 10,000 layers of interleaved graphene separated by 9,999 layers of HfO. Odd layers of the graphene are electrically connected to a first terminal and even layers of graphene are electrically connected to a second terminal of the capacitor device.

Abstract: Described is an improved approach to implement routing for electrical designs. A structural routing solution is provided, where an automatic routing mechanism is implemented to generate a complete routing tree, and specific portions of the design are routed individually from other portions of the design.

Abstract: Monitoring signals in an integrated circuit can include monitoring a probed signal of an integrated circuit using a logic analyzer circuit implemented within the integrated circuit, detecting state changes in the probed signal using the logic analyzer circuit, and generating, within the logic analyzer circuit, a file specifying time stamped state changes of the probed signal.

Abstract: A computer implemented method for increasing scalability in bounded liveness verification includes receiving, by one or more processors, a counterexample trace showing a bounded liveness failure and a set of parameters associated with the counterexample trace, partitioning the counterexample trace into segments representing bound increments contributing to the bounded liveness failure, selecting, by one or more processors, a time interval during which to repeat input values, wherein the selected time interval correlates to one or more segments, evaluating, by one or more processors, the received counterexample after repeating the selected time interval, determining, by one or more processors, whether the evaluation indicates that the counterexample falsifies a deeper bound with respect to a bound or an unbounded liveness counterexample, and, responsive to determining the evaluation indicates that the counterexample falsifies a deeper bound, providing, by one or more processors, counterexample falsification re