Abstract: The present disclosure relates to a computer-implemented method for use in an electronic circuit design. Embodiments may include receiving, using at least one processor, the electronic circuit design and displaying, via a graphical user interface, a first device associated with the electronic circuit design. Embodiments may further include displaying, via the graphical user interface, a second device associated with the electronic circuit design. Embodiments may also include displaying, via the graphical user interface, inter-device connectivity between the first device and the second device and displaying intra-device connectivity between at least one of the first device and the second device, wherein the inter-device connectivity and the intra-device connectivity are visibly distinct.

Abstract: A method for calculating cell edge leakage in a semiconductor device comprising performing a device leakage simulation to obtain leakage information for different cell edge conditions and providing attributes associated with cell edges in the semiconductor device. The method further comprises performing an analysis to identify cell abutment cases present in the semiconductor device and calculating the leakage of the semiconductor device based at least in part on probabilities associated with the cell abutment cases and the simulated leakage values obtained from the device leakage simulation.

Abstract: The present disclosure relates to a system for use in electronic circuit design. The system may include a computing device configured to receive, using at least one processor, an electronic design. The at least one processor may be further configured to generate a common path pessimism removal (“cppr”) database configured to store one or more cppr tags obtained from an initial timing analysis of at least a portion of the electronic design. The at least one processor may be further configured to apply the one or more cppr tags during a block-level timing analysis.

Abstract: A computer-implemented method generates a plurality of clusters based on components included in a design under test (DUT); classifies a subset of clusters of the plurality of clusters as tangled clusters; modifies at least two tangled clusters of the subset of clusters based on overlap between the at least two tangled clusters; determines, for each tangled cluster in the subset of clusters, a gate count based on the interconnectivity of the tangled cluster; and partitions the DUT among a plurality of field-programmable gate arrays (FPGAs) based on the gate count determined for each tangled cluster from the subset of clusters.

Abstract: Embodiments relate to a method and computer program for determining a placement of at least one circuit for a reconfigurable logic device. The method comprises obtaining (110) information related to the at least one circuit. The at least one circuit comprises a plurality of blocks and a plurality of connections between the plurality of blocks. The plurality of blocks comprise a plurality of logic blocks. The method further comprises calculating (120) a circuit graph based on the information related to the at least one circuit. The circuit graph comprises a plurality of nodes and a plurality of edges. The plurality of nodes represent at least a subset of the plurality of blocks of the at least one circuit and wherein the plurality of edges represent at least a subset of the plurality of connections between the plurality of blocks of the at least one circuit. The method further comprises determining (130) a force-directed layout of the circuit graph.

Abstract: A method of exhaustively verifying a property of a hardware design to implement a floating point power function. The method includes, formally verifying that the hardware design is recurrent over sets of ? input exponents, wherein ? is an integer that is a multiple of the reciprocal of the exponent of the power function; and for each recurrent input range of the hardware design, exhaustively simulating the hardware design over a simulation range to verify the property is true over the simulation range, wherein the simulation range comprises only ? input exponents.

Abstract: The present disclosure relates to a method for use in a formal verification of an electronic design. Embodiments may include providing, using at least one processor, an electronic design and performing formal verification of at least a portion of the electronic design having an original property. Embodiments may further include analyzing at least one output net bit associated with a check of the electronic design. Embodiments may also include generating a structural observability expression, based upon, at least in part, the at least one output net bit and setting the structural observability expression as a precondition to the original property.

Abstract: A hybrid battery system is provided for extending the shelf-life of rechargeable batteries. The hybrid battery system may contain sets of non-rechargeable and rechargeable batteries respectively. As the rechargeable batteries are discharged (e.g., from self-discharge), the hybrid battery system may utilize the non-rechargeable batteries to maintain the rechargeable batteries at a preferred state of charge. A preferred state of charge may be selected to extend the shelf-life of the rechargeable batteries. Alternatively, a signal may change the preferred state of charge to prepare the rechargeable batteries for use or for other reasons. The hybrid battery system may contain modular components, thereby allowing for easy replacement of defective or otherwise unsuitable non-rechargeable batteries, rechargeable batteries, or supporting electronics.

Abstract: The present embodiments are directed generally to techniques for providing an interactive environment that gives visual feedback and indicators to identify and/or encourage effective sharing of partially used drill sites, all inside a typical etch-edit environment. Such an interactive environment allows designers to effectively leverage and exploit new PCB manufacturing techniques that allow for multi-net use of a single drill hole.

Abstract: The present disclosure relates to a system and method for electronic design recommendations. Embodiments may include receiving, using at least one processor, an electronic design. Embodiments may further include recognizing one or more circuits within the electronic circuit design. Embodiments may also include identifying one or more user-specific circuit performance preferences. Embodiments may further include generating a first set of one or more placement and routing topology recommendations based upon, at least in part, the one or more user-specific circuit performance preferences. Embodiments may also include receiving a selection of at least one of the placement and routing topology recommendations. Embodiments may further include generating a second set of one or more placement and routing topology recommendations based upon, at least in part, the selected at least one placement and routing topology recommendations.

Abstract: An electronic device is disclosed. The disclosed electronic device includes a display, a charging circuit that transmits and receives power to and from an external electronic device, a sensor circuit that senses a spatial relationship of the electronic device with the external electronic device, a processor that is electrically connected with the display, the charging circuit, and the sensor circuit. When wirelessly transmitting or receiving power to or from the external electronic device using the charging circuit, the processor may transmit and receive information associated with the wireless transmission or reception of power and display the information based on the spatial relationship.

Abstract: An approach is described for yield calculation using statistical timing data that accounts for path and stage delay correlation. Embodiments of the present invention provide an improved approach for yield calculation using statistical timing data that accounts for path and stage delay correlation. According to some embodiments, the approach includes receiving statistical timing analysis data, identifying paths for performing timing analysis, performing timing analysis where common segments of different paths are analyzed using shared data and where subsequent stages are transformed to provide an expected correlation between stages, and generating yield probability results based on at least the results of calculating timing analysis.

Abstract: The invention relates to a method and a device for generating a reference image in the characterization of a mask for microlithography, wherein the mask comprises a plurality of structures and wherein the reference image is generated by simulation of the imaging of said mask, said imaging being effected by a given optical system, both using a rigorous simulation and using a Kirchhoff simulation, wherein the method comprises the following steps: assigning each structure of said plurality of structures either to a first category or to a second category, calculating a plurality of first partial spectra for structures of the first category with implementation of rigorous simulations, calculating a second partial spectrum for structures of the second category with implementation of a Kirchhoff simulation, generating a hybrid spectrum on the basis of the first partial spectra and the second partial spectrum, and generating the reference image with implementation of an optical forward propagation of said hybrid spec

Abstract: An approach is described for efficient and accurate signal electromigration analysis of digital-on-top designs with complex interface pin shapes. According to some embodiments, the approach includes performance of parasitic analysis for the interface between nets and primitive/macro cell (blocks). Specifically, the approach includes performing parasitic analysis based on actual location information corresponding to overlap/connection between ports within blocks, external net connections to the ports, and internal net (block net) connections to the port. Thus, by determining the actual locations of the connections (as opposed to a presumed location) the parasitic effects associated with the ports and the connections thereof can be calculated.

Abstract: Provided is a charging system characterized by being provided with: a mobile device including a first NFC antenna and a rechargeable battery which is charged on the basis of a current induced in the first NFC antenna by electromagnetic induction; and a charger including a second NFC antenna which causes electromagnetic induction to be induced in the first NFC antenna, and a supply unit which supplies the second NFC antenna with a feed current for inducing the electromagnetic induction; and in that the charging system is further provided with a control means for causing an intended electromagnetic induction to arise between the first NFC antenna and the second NFC antenna.

Abstract: Embodiments of the present disclosure may include receiving, using a processor, an ASCII file including timing and power parameters associated with a portion of the electronic circuit design. Embodiments may further include analyzing the ASCII file and displaying, at a graphical user interface, information from the ASCII file. Embodiments may also include parsing, via the graphical user interface, the information using one or more user-selectable parameters.

Abstract: An example circuit includes: a first clock gating circuit coupled between a first latch and a second latch and configured to provide a first gated clock signal based at least in part on an input clock signal. The first latch is configured to be activated in response to the first gated clock signal being at a first logic level to pass a data input. The second latch is configured to be activated in response to the input clock signal being at a second logic level to pass a first selection signal.

Abstract: A device includes a charger case. Charging electronics are supported within the case. An electrical connector is coupled to the charging electronics for coupling to a power source. A cooling element is coupled to the charger case and extendable to an extended position from the case such that a cooling surface area of the charger case is increased.

Abstract: A computer-implemented method of manufacturing an integrated circuit includes placing a plurality of standard cells that define the integrated circuit, selecting a timing critical path from among a plurality of timing paths included in the placed standard cells, and selecting at least one net from among a plurality of nets included in the timing critical path as at least one timing critical net. The method further includes pre-routing the at least one timing critical net with an air-gap layer, routing unselected nets, generating a layout using the pre-routed at least one timing critical net and the routed unselected nets, and manufacturing the integrated circuit based on the layout.

Abstract: The invention relates to an integrated circuit comprising: a row of sink cells, a first driver cell, a second driver cell, an interconnect line connecting the first driver cell to the sink cells of the row; and a shunt line connecting the second driver cell to a point between ends of the interconnect line, wherein a segment of the interconnect line between the point and the first driver cell is bigger than 60% of a length the interconnect line and less than 80% of the length of the interconnect line.