Abstract: An electronic-photonic integrated-circuit assembly comprises a carrier substrate (310) and one or more integrated-circuit dies (330, 340) bonded to one another so as to form a die stack with exterior surfaces corresponding to an outer surface of a first one of the integrated-circuit dies and to an outer surface of a second one of the integrated-circuit dies, where at least one of the integrated-circuit dies includes one or more integrated photonic devices. One or more channels or passages (320) are formed into the outer surface of the first one of the integrated-circuit dies, and a first surface of the carrier substrate (310) is bonded to the outer surface of the first one of the integrated-circuit dies, thereby enclosing the one or more channels or passages (320), The integrated-circuit dies are electrically connected to each other via electrically conductive through-wafer interconnects or electrically conductive through-wafer vias.

Abstract: A semiconductor structure including a bottom source drain region arranged on a substrate, a semiconductor channel region extending vertically upwards from a top surface of the bottom source drain region, a metal gate disposed on and around the semiconductor channel region, and a top source drain region above the semiconductor channel region and comprising a first doped epitaxy region and a second doped epitaxy region.

Abstract: In a manufacturing method of a semiconductor device including a substrate having a front surface and a rear surface, and a film attached to the rear surface, the film is attached on the rear surface, a rear surface side groove is provided by half-cutting the substrate from the rear surface together with the film, a protective member is attached to the film after the rear surface side groove is provided, and a front surface side groove connected to the rear surface side groove is provided by dicing the substrate from the front surface after the protective member is attached.

Abstract: A semiconductor device includes gate electrodes spaced apart from each other in a first direction perpendicular to a substrate's upper surface, and extending by different lengths in a second direction perpendicular to the first direction. The device further includes first and second channels penetrating the gate electrodes and extending in the first direction, a horizontal portion disposed in lower portions of the gate electrodes and connecting lower portions of the first and second channels to each other, and a source line disposed in an upper portion of the second channel and connected to the second channel. The gate electrodes include memory cell electrodes included in memory cells, a first ground select electrode disposed in lower portions of the memory cell electrodes, a second ground select electrode disposed in upper portions of the memory cell electrodes, and a string select electrode disposed in upper portions of the memory cell electrodes.

Abstract: A method for producing a sealed optical semiconductor device makes it possible to seal an optical semiconductor element using a sealing film. The method includes: placing a sealing film on an optical semiconductor element substrate on which an optical semiconductor element is placed within a pressure reduction chamber, and the pressure within the chamber is reduced; heating the film where at least the periphery of the film is thermally fused to the surface of the optical semiconductor element placement substrate; and a step in which the reduction of pressure within the chamber is released and the optical semiconductor element placement substrate is sealed by the film. The temperature T2 of the optical semiconductor element placement substrate when the reduction of pressure within the chamber is released is a temperature at which the film exhibits a tensile strength of 0.02-0.15 MPa and an elongation at break of 150-450%.

Abstract: A method for forming a semiconductor structure is disclosed. A substrate having a logic device region and a memory device region is provided. A first dielectric layer is formed on the substrate. Plural memory stack structures are formed on the first dielectric layer on the memory device region. An insulating layer is formed and conformally covers the memory stack structures and the first dielectric layer. An etching back process is performed to remove a portion of the insulating layer without exposing any portion of the memory stack structures. After the etching back process, a second dielectric layer is formed on the insulating layer and completely fills the spaces between the memory stack structures.

Abstract: Embodiments of three-dimensional (3D) memory devices and methods for forming the same are disclosed. In an example, a 3D memory device includes a substrate, a gate electrode above the substrate, a blocking layer on the gate electrode, a plurality of charge trapping layers on the blocking layer, a tunneling layer on the plurality of charge trapping layers, and a plurality of channel layers on the tunneling layer. The plurality of charge trapping layers are discrete and disposed at different levels. The plurality of channel layers are discrete and disposed at different levels. Each of the channel layers corresponds to a respective one of the charge trapping layers.

Abstract: A method of forming a semiconductor structure includes forming a first portion of a source/drain contact over a source/drain region of a fin-type field-effect transistor (FinFET), the source/drain region being formed over a fin providing a channel region of the FinFET and being adjacent a gate spacer surrounding a gate region of the FinFET. The method also includes forming a first interlayer dielectric (ILD) layer over the first portion of the source/drain contact, the gate spacer and the gate region, and forming a second ILD layer over the first ILD layer. The method further includes forming a second portion of the source/drain contact over the first portion of the source/drain contact in a first opening in the first ILD layer, and forming a third portion of the source/drain contact over the second portion of the source/drain contact in a second opening in the second ILD layer. The second opening is larger than the first opening.

Abstract: A semiconductor device package includes a first semiconductor device, a first redistribution layer (RDL) structure and a second RDL structure. The first semiconductor device has a first conductive terminal and a second conductive terminal. The first RDL structure covers the first conductive terminal. The second RDL structure covers the second conductive terminal and being separated from the first RDL structure.

Abstract: Embodiments disclosed herein relate generally to forming a gate layer in high aspect ratio trenches using a cyclic deposition-treatment process. In an embodiment, a method includes subjecting a substrate surface having at least one feature to a film deposition process to form a conformal film over a bottom surface and along sidewall surfaces of the feature, subjecting the substrate surface to a treatment process to form respective halogen surface layers or respective halogen-terminated layers on the conformal film formed at respective upper portions of the sidewall surfaces, and performing sequentially and repeatedly the film deposition process and the treatment process to fill the feature with the film.

Abstract: A method of producing an optoelectronic semiconductor component includes A) providing at least three source substrates, wherein each of the source substrates is equipped with a specific type of radiation-emitting semiconductor chips, B) providing a target substrate having a mounting plane configured to mount the semiconductor chips thereto, C) forming platforms on the target substrate, and D) transferring at least some of the semiconductor chips with a wafer-to-wafer process from the source substrates onto the target substrate so that the semiconductor chips transferred to the target substrate maintain their relative position with respect to one another, within the types of semiconductor chips, wherein on the target substrate the semiconductor chips of each type of semiconductor chips have a specific height above the mounting plane due to the platforms so that the semiconductor chips of different types of semiconductor chips have different heights.

Abstract: A light emitting device includes a substrate, and a laminated structure provided on the substrate, wherein the laminated structure has a plurality of columnar portions, the columnar portion contains a material having a wurtzite-type crystal structure, in a plan view as seen from a layered direction of the laminated structure, the plurality of columnar portions are arranged in a square lattice form or rectangular lattice form, a line passing through centers of the adjacent columnar portions is inclined relative to m-planes of the columnar portions located between the centers of the adjacent columnar portions, and vertices of the adjacent columnar portions are not placed on the line.

Abstract: A semiconductor memory device includes a semiconductor substrate including a diode formed in an upper layer portion of the semiconductor substrate, a first insulating film provided above the semiconductor substrate, a first conductive film provided above the first insulating film and coupled to the diode, a stacked body provided above the first conductive film, an insulator and an electrode film being stacked alternately in the stacked body, a semiconductor member piercing the stacked body and being connected to the first conductive film, and a charge storage member provided between the electrode film and the semiconductor member.

Abstract: This invention provides a semiconductor device and a manufacturing method thereof.

Abstract: A semiconductor memory device according to embodiments described herein, includes a first stacked body, a second stacked body, a first memory hole, a second memory hole, and a joint. In the first stacked body, a plurality of first conductive layers and a plurality of first insulating layers are alternately stacked. The second stacked body is disposed above the first stacked body, and a plurality of second conductive layers and a plurality of second insulating layers are alternately stacked therein. The first memory hole extends in the first stacked body in a first direction that is a stacking direction of the first stacked body. The second memory hole extends in the second stacked body in the first direction. The joint communicates the first memory hole and the second memory hole. The joint includes an inner wall surface and a sidewall insulating layer. The inner wall surface has a plane continuous with the inner wall of the first memory hole.

Abstract: A method may include filling a via opening with a spacer, the via opening formed in a dielectric layer, forming a trench within the spacer, filling the trench with a metal layer, recessing the spacer to form an opening and expose an upper portion of the metal layer, wherein the exposed portion of the metal layer is formed into a cone shaped tip, conformally depositing a liner along a bottom and a sidewall of the opening and the exposed portion of the metal layer, depositing a second dielectric layer along the bottom of the opening on top of the liner, recessing the liner to form a channel and partially exposing a sidewall of the second dielectric layer and a sidewall of the metal layer, depositing a third dielectric layer in the channel, and depositing a phase change memory layer within the opening.

Abstract: Stack assembly having electro-acoustic device. In some embodiments, a radio-frequency (RF) module can include a packaging substrate configured to receive a plurality of components, and an electro-acoustic device mounted on the packaging substrate. The RF module can further include a die having an integrated circuit and mounted over the electro-acoustic device to form a stack assembly. The electro-acoustic device can be, for example, a filter device such as a surface acoustic wave filter. The die can be, for example an amplifier die such as a low-noise amplifier implemented on a silicon die.

Abstract: A light-emitting device has enhanced light output by employing a reflective optical cavity along the bank structure to improve light extraction. The light-emitting device includes a bank structure; an emissive cavity disposed within the bank structure; a filler material layer disposed within the bank structure and on a light-emitting side of the emissive cavity; and a reflective optical cavity disposed along an inner surface of the bank structure facing the filler material layer. The reflective optical cavity is configured to out-couple light that is internally reflected by an emitting side surface of the filler material layer and is incident on the reflective optical cavity. The reflective optical cavity incudes a first conductive layer and a second conductive layer that are separated by a non-conductive dielectric layer.

Abstract: A method includes providing a first layer of epitaxial silicon carbide supported by a silicon carbide substrate, providing a second layer of epitaxial silicon carbide on the first layer, forming a plurality of semiconductor devices in the second layer, and separating the substrate from the second layer at the first layer. The first layer includes a plurality of voids.

Abstract: Provided are an organic light-emitting diode display panel and a manufacturing method thereof, and a display device, in the field of display technology. The OLED display panel includes: a base substrate and plurality of light-emitting units. Each light-emitting unit includes a first electrode, a second electrode, and a light-emitting layer between the first electrode and the second electrode, and a ratio of areas of light-emitting layers in the plurality of light-emitting units is within a threshold range.