Abstract: A radio-frequency switch is disclosed, comprising a set of field-effect transistors disposed between a first node and a second node. In some embodiments, each field-effect transistor of the set of field-effect transistors has a respective source, drain, gate, and body. In some embodiments, the radio-frequency switch includes a compensation circuit coupled in parallel with the set of field-effect transistors, the compensation circuit configured to compensate a non-linearity effect generated by the set of field-effect transistors.

Abstract: A gate driver circuit comprises a sensor, an amplifier, a regulator and a gate driver. The sensor is configured to sense a collector-emitter voltage and includes a first resistor and a second resistor connected in series, a high voltage diode connected between the series connected first and second resistors and a first capacitor connected parallel to the second resistor. The amplifier is configured to amplify a sensor output voltage and includes a non-inverting operational amplifier controlled by means of a plurality of resistors, a voltage follower connected to an output terminal of the non-inverting operational amplifier through a first diode and a third resistor connected across the first diode and the voltage follower. The regulator is configured to regulate a regulator output voltage based on an amplifier voltage. The gate driver is configured to connect/disconnect the regulator output voltage to the base terminal of the BJT.

Abstract: A nonvolatile storage device includes a power management system with a power loss imminent (PLI) capacitor to provide backup energy in case system power is lost. The power management system includes a circuit with a charging path for the PLI capacitor that includes a series current-limiting circuit, and a diode coupled in parallel with the current-limiting circuit, the diode having a cathode coupled to the charging circuit and an anode to couple to the PLI capacitor.

Abstract: A power supply circuit of a passenger conveyor converts includes an electrolytic capacitor and a control power supply device configured to supply an electric power to a charging circuit configured to charge the electrolytic capacitor. A storage battery is disposed between a converter and an inverter in parallel with the electrolytic capacitor. When an operation of the passenger conveyor is stopped in response to a key operation, the power supply to the control power supply device is shut off. When the operation of the passenger conveyor is resumed in response to a key operation, a DC electric power charged in the storage battery is supplied to the inverter, to thereby allow the passenger conveyor to resume the operation.

Abstract: The invention is notably directed to a method of operating a superconducting channel. The method relies on a device including: a potentially superconducting material; a gate electrode; and an electrically insulating medium. A channel is defined by the potentially superconducting material. The gate electrode positioned adjacent to the channel, such that an end surface of the gate electrode faces a portion of the channel. The electrically insulating medium is arranged in such a manner that it electrically insulates the gate electrode from the channel. Rendering the channel superconducting by cooling down the device. Next, a voltage difference is applied between the gate electrode and the channel to inject electrons in the channel through the electrically insulating medium and thereby generate a gate current between the gate electrode and the channel. The electrons are injected with an average energy sufficient to modify a critical current IC of the channel.

Abstract: A driving method and a driving device using the same are disclosed. The driving method controls a pulse transformer. The secondary winding of the pulse transformer is electrically connected to a control device. Firstly, positive charging electrical energy is delivered to the primary winding, thereby charging the control device. Then, the control device is disconnected from the secondary winding while the primary winding is in a high-impedance state. Finally, negative discharging electrical energy is delivered to the primary winding and the control device is electrically connected to the secondary winding, thereby discharging the control device, and the primary winding is in a low-impedance state after the step of delivering the negative discharging electrical energy to the primary winding.

Abstract: A circuit for regenerative gate charging includes an inductor coupled to a gate of a FET. An output control circuit is coupled to a timing control circuit and a bridged inductor driver, which is coupled to the inductor. A sense circuit is coupled to the gate and to the timing control circuit, which receives a control signal, generates output control signals in accordance with a first switch timing profile, and transmits the output control signals to the output control circuit. In accordance with the first switch timing profile, the output control circuit holds switches of the bridged inductor driver in an ON state for a first period and holds all of the switches in an OFF state for a second period. Gate voltages are sampled during the second period and after the first period. The timing control circuit generates a second switch timing profile using the sampled voltages.

Abstract: Methods, systems, and apparatus, including for back-up power sources. In one aspect, a method includes providing a plurality of first battery devices, each first battery device respectively electrically coupled to a respective server rack in a plurality of server racks and having a respective capacity to provide power to the respective rack for a power anomaly for up to a first duration. Providing a second battery device electrically coupled to the plurality of server racks and having a capacity to provide power to the plurality of respective server racks for a power anomaly for up to a second duration, wherein the second duration is longer than the first duration. A power anomaly is a deviation of mains power from one or more of a nominal supply voltage and frequency.

Abstract: A space-based solar power station, a power generating satellite module and/or a method for collecting solar radiation and transmitting power generated using electrical current produced therefrom is provided. Power transmitters can be coordinated as a phased array and the power generated by the phased array is transmitted to one or more power receivers to achieve remote wireless power generation and delivery. In many embodiments, a reference signal is distributed within the space-based solar power station to coordinate the phased array. In several embodiments, determinations of the relative locations of the antennas in the array are utilized to evaluate the phase shift and/or amplitude modulation to apply the reference signal at each power transmitter.

Abstract: A charge pump includes: (I) a current source; (II) a p-channel source current network including: a first p-channel transistor; a second p-channel transistor; a p-channel current switch including at least one source terminal coupled to the drain terminal of the first p-channel transistor, at least one gate coupled to a phase comparator, and at least one drain terminal; a third p-channel transistor; and (III) a n-channel sink current network including: a first n-channel transistor; a second n-channel transistor; a third n-channel transistor; a n-channel current switch comprising at least one drain terminal coupled to the source terminal of the third n-channel transistor, at least one gate coupled to the phase comparator; and at least one source terminal coupled to the drain terminal of the first n-channel transistor; and wherein the p-channel source current network and the n-channel sink current network draw a baseline current from the first p-channel transistor.

Abstract: Methods and apparatuses of a two-phase flip-flop with symmetrical rise and fall times are disclosed herein. An example apparatus may include a clock generator circuit including a two-phase flip-flop circuit configured to provide an output signal. The two-phase flip-flop circuit includes a two-phase flip-flop and a driver circuit. The two-phase flip-flop is configured to provide a first driver control signal and a second driver control signal responsive to a clock signal. The first driver control signal and the second driver control signal are complementary. The driver circuit is configured to provide the output signal responsive to the first driver control signal and the second driver control signal.

Abstract: A switching apparatus for carrying and disconnecting electric currents includes: a first mechanical contact arrangement; a second mechanical contact arrangement which is connected in series with the first mechanical contact arrangement; a semiconductor switch which is connected in parallel to the first mechanical contact arrangement; a switching electronics system for switching on and switching off the semiconductor switch; and a control circuit for ascertaining a voltage across the first mechanical contact arrangement as an ascertained voltage and generating an actuation signal for the switching electronics system, which actuation signal switches on the semiconductor switch, depending on the ascertained voltage. During a switching process, the switching apparatus closes the two mechanical contact arrangements with a time delay in relation to one another.

Abstract: A configurable clock buffer including first and second buffers and isolation circuitry. The first buffer has an input coupled to a clock input node and has an output coupled to a clock output node. The second buffer has an input coupled to an intermediate input node and has an output coupled to an intermediate output node. The isolation circuitry is responsive to at least one mode signal, in which it electrically couples the intermediate input node to the clock input node and electrically couples the intermediate output node to the clock output node when the at least one mode signal is in a first state, and in which it electrically couples the intermediate input node to a static node and electrically isolates the intermediate output node from the clock output node when the at least one mode signal is in a second state.

Abstract: A high speed signal drive circuit includes a D-PHY drive signal generation module, a C-PHY drive signal generation module, a drive signal selection module and a multiplex drive module. An output terminal of the D-PHY drive signal generation module and an output terminal of the C-PHY drive signal generation module are both connected to an input terminal of the drive signal selection module. An output terminal of the drive signal selection module is connected to an input terminal of the multiplex drive module. The drive signal selection module controls control switches of the multiplex drive module to be on and off based on a D-PHY drive signal or a C-PHY drive signal, so that the multiplex drive module functions as a D-PHY drive circuit or a C-PHY drive circuit. Thus, dual functions of the D-PHY drive circuit and the C-PHY drive circuit can be realized.

Abstract: A switched-capacitor DC-DC power converter circuit is provided. The switched-capacitor DC-DC power converter circuit includes N input-side switched capacitor units and N output-side switched capacitor units. There is a charge recycling phase located between two adjacent conversion phases. In the 2N conversion phases, a bottom end of a capacitor of at least one of the input-side switched capacitor units and a bottom end of a capacitor of at least one of N output-side switched capacitor units is selectively electrically connected to an output terminal of the switched-capacitor DC-DC power converter circuit. In each charge recycling phase, bottom ends of two capacitors of N input-side switched capacitor units and N output-side switched capacitor units are electrically connected to each other through two of the input-side charge recycle switches and output-side charge recycle switches.

Abstract: A driver includes an open drain output transistor, a capacitor, a first current source, and first and second transistors. Upon assertion of a transmit signal to turn on the first transistor, a controller asserts a second control signal to turn on the second transistor responsive to a voltage of the capacitor being less than a threshold voltage of the open drain output transistor to thereby increase the control terminal voltage for the open drain output transistor at a first time rate. The controller deasserts the second control signal to turn off the second transistor responsive to the capacitor voltage exceeding the threshold voltage. Responsive to the capacitor's voltage exceeding the threshold, the first current source charges the capacitor to further increase the control terminal voltage at a second time rate that is smaller than the first time rate.

Abstract: A phase-locked loop (PLL) and a method for calibrating a VCO therein are provided. The PLL comprises a frequency-phase detector, a charge pump, a loop filter, a VCO, a divider and a calibration circuit. The calibration circuit is used to acquire a frequency of an output signal of the VCO, to calibrate the frequency of the output signal according to an expected frequency, and to acquire frequency control parameters of the VCO at the current signal frequency. The amplitude and gain of the output signal are kept constant according to the amplitude control parameters and gain control parameters. The PLL can meet the demands on frequencies of multiple protocols and can adaptively look up and stabilize the suitable frequency. It solves the issue that the amplitude of the output signal of the VCO is not constant when the PLL operates in a large frequency range.

Abstract: A spur measurement system uses a first device with a spur cancellation circuit that cancel spurs responsive to a frequency control word identifying a spurious tone of interest. A device under test generates a clock signal and supplies the clock signal to the first device through an optional divider. The spur cancellation circuit in the first device generates sine and cosine weights at the spurious tone of interest as part of the spur cancellation process. A first magnitude of the spurious tone in a phase-locked loop in the first device is determined according to the sine and cosine weights and a second magnitude of the spurious tone in the clock signal is determined by the first magnitude divided by gains associated with the first device.

Abstract: A differential output driver circuit includes a drive path having a first output node that provides a first output differential signal and a second output node that provides a complementary second output differential signal to the first output differential signal, a current control transistor to control current of the drive path, and a current measurement resistor circuit located in the drive current path outside of a path segment between the first and second output node. Current flowing through the drive path flows through the current measurement resistor circuit, and a voltage across the current measurement resistor circuit is indicative of an amount of current flowing through the drive path. A transistor control circuit utilizes a voltage across the current measurement resistor circuit to control a control terminal of the current control transistor to control the current in the drive path based on the voltage across the current measurement resistor circuit.

Abstract: A charge pump circuit generates a charge pump output signal at a first node and is enabled by a charge pump control signal. A diode has first and second terminals coupled to first and second nodes. A comparator has an inverting input coupled to the second node and a non-inverting input coupled to a third node, and causes generation of the charge pump control signal. A first current mirror produces a first current at the second node, and a second current mirror produces a second current (equal in magnitude to the first current) at the third node. The first terminal and second terminals may be a cathode and an anode. The first current mirror may be a current sink sinking a first current from the second node. The second current mirror may be current source sourcing a second current (equal in magnitude to the first current) to the third node.