Abstract: A fully self-sufficient configurable spare gate cell that has two types of inputs: a functional input bus and an equation input bus, whereby the spare gate cell can be transformed into any sum of product operator by the assertion of certain signals to the equation input bus. In a spare state, the functional input buses are connected to an area of pre-defined logic where the need for bug fixes are high. Thus, the spare cell would be automatically placed close to the bug-fix area during the place-and-route phase of chip design, thereby reducing the need to look for routing channels.

Abstract: The disclosed A/D conversion system is designed to signal the beginning or the impending beginning of an A/D conversion and/or to request the implementation of an A/D conversion from another A/D converter. As a result, it is possible to have a plurality of A/D converters work absolutely time-synchronously with minimal outlay.

Abstract: A voltage margin setting interface circuit has a single input pin, and is configured to program the slew rate and polarity direction of variation of the operation of a digital-to-analog converter, such as may be used to set a reference voltage level, for application to an error amplifier of a voltage regulator circuit of the power supply of a personal computer. A DAC clocking control circuit is coupled to an output port, and to respective DAC increment and decrement ports, and is operative to control the magnitude of output current, and to assert an output signal at one of the increment and decrement ports, in accordance with a prescribed relationship between the voltage and upper and lower ranges of the input voltage relative to its middle value.

Abstract: Integrated circuit devices include data inversion circuits therein that are configured to evaluate at least first and second ordered groups of input data in parallel with an ordered group of output data previously generated by the data inversion circuit. The data inversion circuit is further configured to generate inverted versions of the first and second ordered groups of input data whenever a number of bit differences between the first ordered group of input data and the ordered group of output data is greater than one-half a size of the first ordered group of input data and a number of bit differences between the second ordered group of input data and the inverted version of the first ordered group of input data is greater than one-half a size of the second ordered group of input data, respectively.

Abstract: An N-bit analog to digital converter includes a reference ladder connected to an imput voltage at one end, and to ground at another end, an array of differential amplifiers whose differential inputs are connected to taps from the reference ladder, wherein each amplifier has a first differential input connected to the same tap as a neighboring amplifier, and a second differential imput shifted one tap from the neighboring amplifier, and an encoder that converts outputs the array to an N-bit output.

Abstract: A dielectric filter includes a dielectric block having inner-conductor-formed holes extending from a first face of the dielectric block to a second face opposed to the first face. Inner conductors are formed inside the inner-conductor-formed holes such that both ends of the inner-conductor-formed holes are open-circuited. On the exterior surface of the dielectric block, balanced input/output terminals are capacitively coupled to the open ends of the inner-conductor-formed holes. A metal cover is provided so as to cover one of the first or second face of the dielectric block. The metal cover functions as a short-circuit conductor in a spurious mode such as a TE mode other than a TEM mode, and hence the influence of the spurious mode is avoided.

Abstract: An end-surface reflection type surface acoustic wave filter is capable of increasing an attenuation amount outside a pass band while insertion loss characteristics are not seriously deteriorated. The filter is a longitudinally coupled resonator type surface acoustic wave filter using an SH type surface acoustic wave, which has first and second grooves formed in a piezoelectric substrate at the top surface thereof so as to be substantially parallel to each other and spaced from each other by a predetermined distance. In addition, IDTs which are provided between the grooves for defining the longitudinally coupled resonator type surface acoustic wave filter, reflection end-surfaces disposed on side surfaces of the first and the second grooves at the IDT sides, and one of a resin-coating layer and a protective layer made of SiO2, are provided on the top surface of the piezoelectric substrate.

Abstract: A method, system, and apparatus for remotely calibrating data symbols received by a radio frequency identification (RFID) tag population are described. Tags are interrogated by a reader, which may be located in a network of readers. The reader transmits data symbols to the tags. Tags respond to the interrogations with symbols that each represent one or more bits of data. To calibrate the tags, the reader transmits a plurality of pulses of different lengths to the tag population. The tags receive the plurality of pulses. A characteristic of each pulse, such as a pulse length, is stored by the tags. The stored pulse lengths are used to define different data symbols that are subsequently received by the tags from the reader.

Abstract: An auto-calibration technique for optimizing the transfer function of analog-to-digital converters. The technique can be applied to analog-to-digital converter (ADC) architectures employing a cascade of n-stages to form a composite n-bit ADC transfer function. The technique utilizes evaluation of the probability density function of individual bits to determine error sign, minimize error magnitude and assure calibration convergence.

Abstract: An RF filter that includes a substrate having a plurality of regions, each having respective substrate properties including a relative permeability and a relative permittivity. At least one filter section is coupled to one of the regions of the substrate which has different substrate properties in comparison to other regions. Other filter sections can be coupled to other substrate regions having different substrate properties. The permeability and/or permittivity can be controlled by the addition of meta-materials to the substrate and/or by the creation of voids in the substrate. The RF filter can be a stepped impedance filter. One filter section includes a transmission line section having an impedance influenced by the region of the substrate on which the filter section is disposed. The transmission line section construction can be a microstrip, buried microstrip, or stripline. A supplemental layer of the substrate can be disposed beneath the filter section.

Abstract: A digital to analog converter (DAC) can comprise: an escalator code generator; and an escalator-code-to-analog converter (ECAC). The generator can (1) represent base 10 numbers with a mixed code having a coin code portion and a cash code portion, which will eliminate multi-bit changes in the cash code upon changes in count direction; and (2) represent a count in a first direction as the sum of the coin code and the cash code. The generator can alter the coin code when the count changes direction while the cash code remains the same until a count capacity of the coin code is exceeded, at which point the cash code can be altered. Cycling between adjacent base 10 numbers is absorbed by the coin code while keeping the cash code the same, which reduces noise introduced into an output of the ECAC due to such cycling.

Abstract: A symbol string detection unit detects the second symbol string matching the first symbol string having a predetermined length n from input character strings. A matching length detection unit detects a matching length k between the third symbol string following the first symbol string and the fourth symbol string following the second symbol string. A coding unit codes an input symbol string based on the symbol string detected by the symbol string detection unit and the matching length k detected by the matching length detection unit.

Abstract: Analog-to-digital converter (ADC) structures and methods are provided that reduce an initial converter nonlinearity by introducing an inverse nonlinearity into the converter's response that is substantially the inverse of the initial converter nonlinearity. In a pipelined ADC embodiment, for example, upstream converter stages are selected that generate an upstream digital code which defines sufficient upstream code words to designate respective segments of the inverse nonlinearity. In response to each of the upstream code words, the conversion gain of the remaining downstream converter stages is then sufficiently adjusted to insert the inverse nonlinearity into the converter response.

Abstract: The present invention is directed to a buffer having dual thresholds. The buffer has an input terminal and an output terminal and comprises a current source, first through fourth transistors, a current mirror, and an output driver. The buffer uses an “analog” topology to achieve accurate buffering when the thresholds of applied signals are not centered about the mid-supply range. The buffer is useful (among other circuits) in analog and mixed circuit integrated circuits that have relatively high voltage supply levels and signals having logic thresholds that are not centered about the mid-supply level. The buffer uses feedback from the output to achieve hysteresis.

Abstract: In a dielectric block, an array of three excitation holes, in each of which one opening is a short-circuited end and the other opening is an open-circuited end, are disposed so as to be interdigitally coupled and balanced input-output terminals are provided at the opening of the excitation holes at both ends of the array. A resonator hole is provided so as to be coupled to one excitation hole of the excitation holes at either end of the array. Thus, a compact dielectric filter with balanced input-output terminals is constructed.

Abstract: A bandpass sigma-delta modulator using acoustic resonators or micro-mechanical resonators. In order to improve resolution at high frequencies, acoustic resonators or micro-mechanical resonators are utilized in a sigma-delta modulator instead of electronic resonators. The quantized output is fed back using a pair of D/A converters to an input summation device. In fourth order devices, the feed back is to two summation devices in series. Such a sigma-delta modulator is usable in a software defined radio cellular telephone system and in other applications where high-frequency and high-resolution A/D conversion is required.

Abstract: This invention relates to a digital modulation method and apparatus used for recording an audio or video signal, computer data, and etc on a recording medium such as an optical or magneto-optical disc. Data words of m bits are translated into code words of n bits in accordance with a conversion table. The code words satisfy a (d, k) constraint in which at least d “0”s and not more than k “0”s occur between consecutive “1”s. The n-bit code words alternate with p-bit merging words which are selected such that between the leading “1” in the code word following the merging word and the trailing “1” in the merging word are at least d “0”s, and further that between the trailing “1” in the code word preceding the merging word and the leading “1” in the merging word are at least d “0”s.

Abstract: A system and method of creating a highly efficient digital amplifier which can take either analog or digital inputs, and produce a high power accurate representation of the input to drive speakers or other low impedance load is described. The system employs a transition detector and delay unit which allows the comparator of the signal modulator to ignore its inputs for a pre-determined number of subsequent clock cycles once an output transition has been detected. Through the use of faster clocks and variable clock cycle skips upon the comparator's output transition, finer resolution of the feedback's clock period for noise-shaping purposes is achieved. Finer resolution of the clock period allows the present invention to employ a more aggressive noise-shaping than previously possible.

Abstract: In a renormalization processing device of MQ-CODER, the value of an augend register A is calculated by a shift quantity calculating unit without performing loop processing, and the number of left shifts SHIFT_A of A up to the end of renormalization processing is calculated. The renormalization processing device judges whether byteout processing or bytein processing occurs or not, on the basis of the positive or negative sign of (SHIFT_A-CT) and the value of CT. When byteout/bytein processing occurs, the values of a code register C and a free byte counter CT that are immediately before the occurrence of processing are found. When byteout/bytein processing does not occur, the values of C and CT that are after the end of normalization processing are found. If the value of (SHIFT_A-CT) is a positive value after byteout/bytein processing, this value is substituted in SHIFT_A and renormalization processing is performed again.

Abstract: A Sigma-Delta modulator(10) comprises a signal put(34) coupled to a forward filter comprising a series connection of a plurality of N summing stages(28, 30, 32), where N is an integer of at least 2, alternating with a corresponding plurality of integrating stages(40, 42, 44) and an analogue to digital converter(ADC)(18) having an input coupled to an output of the Nth integrating stage(44) and an output. A feedback filter comprises a feedback coupling from the output of the ADC(18) to a digital to analogue converter(DAC)(26) which is coupled to an input of each of the summing stages by way of respective weights(46, 48, 50). Control means(66) including switching means (58, 64) are provided for changing the order of the modulator. To reduce the order and increase the bandwidth, the control means by-passes the first(40) of the integrating stages and uses the second(42) of the integrating stages as a first of the integrating stages and vice versa to increase the order and decrease the bandwidth.