Abstract: Processing signals to record media information includes receiving an analog signal at an analog-to-digital converter, where the analog signal includes media information. The analog-to-digital converter converts the analog signal to a corresponding digital signal, where the digital signal includes a first sequence having a first number of bits. A sigma-delta converter processes the digital signal according to a sigma-delta conversion, where the processed digital signal includes a second sequence having a second number of bits, and where the second number of bits is lower than the first number of bits. The processed digital signal is stored in a digital format in a medium in order to record the media information.

Abstract: Coding section 205 recodes decoded data stored in decoded data storage section 204, data conversion section 206 converts data “0” and “1” output from coding section 205 to “1” and “?1” respectively, sum-of-product calculation section 207 multiplies the data output from data conversion section 206 by the demodulated data (soft decision value) stored in demodulated data storage section 201 and then calculates the sum of the products for 1 TTI and stores the sum-of-product result for each data rate, data rate decision section 208 decides the data rate corresponding to a maximum value of the sum-of-product results as the data rate of the demodulated data. This makes it possible to improve the accuracy of data rate decision and reduce decoding errors of a received signal.

Abstract: A parallel DAC topology reduces systematic linearity errors by offsetting the digital codes inputted to the individual DACs from one another. Linearity errors that would normally add together are thus reduced.

Abstract: A mapper-based variable length coding method and decoding method and apparatuses therefor are provided. The mapper-based variable length coding method includes an inputting step for receiving symbol data to be coded and receiving element type information on the kind of symbol data, a coding step for generating a first code number corresponding to the received symbol data, a mapping step for selecting a second code number mapped with respect to selected element type information in mapping tables formed of second code numbers, each of which is appropriately mapped according to the first code number and the element type information, a codeword extracting step for generating a codeword corresponding to the selected second code number, and an outputting step for outputting the generated codeword. According to the methods and apparatuses, the advantages of a universal variable length code table can be maintained while preventing efficiency lowering of compression coding.

Abstract: According to the preferred exemplary embodiments of the present invention, a transmission line, such as microstrip, is connected to a waveguide using suspended stripline as an intermediate connection. This method results is a very low-loss transition, suitable for active microwave device applications such as low-noise receivers and transmitting devices such as power amplifiers.

Abstract: Improved digital to analog converter (DAC) circuitry incorporating the ability to utilize a single DAC to generate either voltage or current outputs, and the ability to digitally adjust the gain and offset. Previous digital to analog circuitry has been limited to a single type of analog output per DAC and to the use of external precision resistors to set the gain and offset for a single DAC, or a group of DACs. By utilizing the same on-chip circuitry to supply both types of outputs, chip area, power consumption and cost is reduced while offering more flexibility to the customer. The ability to digitally adjust the gain and offset for a group of DACs eliminates the cost of external resistors, lowers the board area, and lowers the assembly cost for the end product. In addition, since gain and offset can be adjusted dynamically, maximum flexibility is provided to the customer.

Abstract: A method and structure for a digital-to-analog converter comprising a voltage source supply; a voltage division stack connected to the voltage source supply; a multiplexer connected to the voltage division stack; a digital circuit connected to the multiplexer; an analog circuit connected to the multiplexer; and an input binary word source connected to the digital circuit, wherein outputs of the digital circuit are input into the analog circuit and converted as analog output. According to the invention, the multiplexer comprises any of an NFET and/or a PFET. The digital-to-analog converter further comprises a capacitor connected to the analog circuit and a binary-weighted tunneling current device connected to the digital circuit. The multiplexer and the capacitor are made of thick oxide (at least 5 nm thick). The tunneling current device outputs tunneling current, wherein the tunneling current is adjusted in proportion to a binary weight of the input binary word source.

Abstract: A modulation apparatus and method for more accurately determining a value of a control bit to be inserted into a data sequence and digital sum value (DSV) control bit generating method in which a data conversion unit supplies modulation-delimiter information including information regarding delimiters of modulation of a data sequence based on a conversion table to a modulation-delimiter detecting unit and supplies to a valid-delimiter detecting unit a DSV-segment-delimiter signal including information regarding a delimiter position of a DSV segment of the data sequence having the DSV control bit. The modulation-delimiter detecting unit detects modulation-delimiter positions based on the modulation-delimiter information supplied thereto and supplies a modulation-delimiter signal to the valid-delimiter detecting unit.

Abstract: An efficient technique for generating accurate on-chip DC reference voltages is based on filtering a digital pulse modulated sequence in order to extract its average value encoding a DC level, A passive on-chip filter is used for simplicity with an all-digital modulator implementation. Modulation is proposed using pulse-width and preferably pulse-density modulation methods. The latter has the advantage of using a significantly smaller filter which translates into a smaller implementation and faster operational settling times. Many digital pulse modulation generators are proposed.

Abstract: The number of pulses of a clock signal CLK-A is circularly counted in a count range from “0” to “7”, and count signals indicating count values are produced. A clock signal CLK-B having a frequency lower than that of the clock signal CLK-A is produced from count signals of “3” and “7”, and data transfer between a high speed operating block operated in synchronization with the clock signal CLK-A and a low speed operating block operated in synchronization with the clock signal CLK-B is performed in synchronization with the clock signal CLK-B to receive input serial data or transmit output serial data. When a stuff bit of universal Serial Bus is detected in the input serial data or is inserted in the output serial data, a cycle of the clock signal CLK-B is lengthened by one cycle of the clock signal CLK-A.

Abstract: Techniques for adjusting the boundary between bytes of data in a serial-to-parallel converter are provided. Bits of serial data are shifted into a first register. Data bytes are then shifted out of the first register along parallel signal lines into a second register. The timing of the parallel load of data from the first register to the second register determines the parallel data byte boundary. The boundary between the parallel data bytes can be shifted using a load enable signal. The phase of the load enable signal can be changed to shift the boundary between data bytes by one or more bits. The parallel data can then be loaded from the second register into a third register. The data output signal of the third register is synchronized to a core clock signal to ensure enough set up and hold time for signals output by the third register.

Abstract: A D/A conversion circuit with a small area is provided. In the D/A conversion circuit, according to a digital signal transmitted from address lines of an address decoder, one of four gradation voltage lines is selected. A circuit including two N-channel TFTs is connected in series to a circuit including two P-channel TFT, and a circuit including the circuits connected in series to each other is connected in parallel to each of the gradation voltage lines. Further, an arrangement of the circuit including the two N-channel TFTs and the circuit including the two P-channel TFTs is reversed for every gradation voltage line. By this, the crossings of wiring lines in the D/A conversion circuit becomes small and the area can be made small.

Abstract: A simplified method for forming passive microwave components, such as a filter, and passive microwave components formed by the method. The method includes forming a ceramic insert having a plurality of resonator regions and then die casting an outer casing of a conductive material about the ceramic insert. Each resonator region has a cavity that may be filled with the conductive material used to die cast the outer casing or, alternatively, may be filled with a resonator rod made of different materials than the encapsulating metal.

Abstract: A symbol string detection unit detects the second symbol string matching the first symbol string having a predetermined length n from input character strings. A matching length detection unit detects a matching length k between the third symbol string following the first symbol string and the fourth symbol string following the second symbol string. A coding unit codes an input symbol string based on the symbol string detected by the symbol string detection unit and the matching length k detected by the matching length detection unit.

Abstract: An analog multiplier 11 raises a base reference voltage “Vref0” to the nth power so that a reference voltage “Vref1” is produced. Analog multipliers 12 and 13 sequentially raise the reference voltage “Vref1” to the nth power so that reference voltages “Vref2” and “Vref3” are produced. Switch groups 38-41 control the reference voltages “Vref0” to “Vref3”, which are then sent to an analog multiplier 14 together with an input voltage “Vin”. A comparator 14 sequentially compares a multiplication result “Vx” of the multiplier 14 with a voltage “Vout” outputted from a sensor circuit 2, so that a digital output value “Dout” is produced. The analog multiplier 14 is set as appropriate.

Abstract: In a method of compressing a lookup table for reducing memory, a non-linear function generating apparatus having a lookup table compressed using the method, and a non-linear function generating method, X-coordinates of the non-linear function are separated into a plurality of sections including steps that have predetermined step sizes. Y-coordinate values corresponding to X-coordinate values are extracted for each step. The Y-coordinate values are stored in predetermined addresses in a memory, wherein the step sizes are different according to the sections. In this manner, memory capacity occupied by the lookup table is reduced.

Abstract: A surface acoustic wave device includes a surface acoustic wave element and a sealing member for sealing the surface acoustic wave element. The surface acoustic wave element has a piezoelectric substrate and an electrode provided on the piezoelectric substrate. The sealing ember is made of a resin or glass. The electrode has an electrode layer made of Al or an Al alloy and includes crystals having a twin structure.

Abstract: An input buffer circuit is made up from: a differential amplifier that receives an input signal from the outside and a reference voltage for determining the level of the input signal; a transistor for a first operating current path for supplying a prescribed first operating current to the differential amplifier and that, by having a prescribed fixed voltage supplied to its gate, is always ON; and at least one transistor for a second operating current path for supplying a second operating current that is greater than the first operating current to the differential amplifier when ON, the transistor for the second operating current path being ON/OFF controlled in accordance with a control signal from the outside.

Abstract: An A/D converter having capacitors of a first array of sampling capacitors weighted in binary code connected between a first common circuit node and an input terminal to be charged to an input voltage with respect to a ground of a signal to be converted, and in accordance with SAR technique are then selectively connected with two differential reference terminals, and at the same time capacitors of a second array equal to the first and all connected to a second node are selectively connected to ground and the lower differential voltage terminal. The two nodes are connected to the respective inputs of a comparator. A logic unit controls the connections of the capacitors of the two arrays in accordance with a predetermined timing program and as a function of the output of the comparator.

Abstract: A thin film resonator which combines a microstrip resonator structure and a coplanar resonator structure to form an integrated resonator structure. The resonant frequency of this resonator structure is independent of the substrate thickness within a certain thickness range. This resonator structure also has a very economical size, as compared to other existing resonator designs. Different coupling configurations between the resonators are shown with the resulting coupling coefficients. Also a two-pole, four-pole and an eight-pole filter are designed using the thin film resonator and the insertion loss and return loss characteristics for various filters are shown.