Abstract: A method, system, and apparatus for remotely calibrating data symbols received by a radio frequency identification (RFID) tag population are described. Tags are interrogated by a reader, which may be located in a network of readers. The reader transmits data symbols to the tags. Tags respond to the interrogations with symbols that each represent one or more bits of data. To calibrate the tags, the reader transmits a plurality of pulses of different lengths to the tag population. The tags receive the plurality of pulses. A characteristic of each pulse, such as a pulse length, is stored by the tags. The stored pulse lengths are used to define different data symbols that are subsequently received by the tags from the reader.

Abstract: A switched capacitor circuit of a pipeline analog to digital converter. The pipeline ADC includes a clock generator, a signal reference circuit, and a plurality of switched capacitor circuit. Each switched capacitor includes an operational amplifier, a first sampling capacitor, a first signal input switch, a first reference input switch, a first reference reset switch, and a first feedback network. A method for operating the switched capacitor circuit includes after the first reference input switch turning off, turning on the first signal input switch to transmit a first input signal to the first sampling capacitor and turning on the first reference reset switch to transmit a common signal to a second terminal of the first reference input switch, turning off the first reference rest switch then turning off the first signal input switch, and after the first signal input switch turning off, turning on the first reference input switch.

Abstract: Digital-to-analog and analog-to-digital conversion are implemented in or using programmable logic. The DAC and ADC circuits may be hardwired in a programmable logic integrated circuit or may be implemented using an intellectual property (IP) core. The IP core would be a series of bits to configure the logic cells and other programmable logic of an integrated circuit to include one or more DACs or ADC, or both on the same integrated circuit. The DAC may be a sigma-delta-modulator-based implementation or a resistor-ladder-based implementation.

Abstract: A digital to analog converter augmented with Direct Charge Transfer (DCT) techniques. A digital to analog converter augmented with DCT and CDS techniques. A digital to analog converter augmented with Postfilter Droop Compensation.

Abstract: Open loop common mode driver for switched capacitor input to SAR. A method for selectively switching capacitors in a SAR capacitor array that have a common plate thereof interfaced to the input of a comparator. The method includes the step of first initiating a SAR compare cycle. Then. the other plates the capacitors switched such that they are disposed at either a first capacitor reference voltage or a second capacitor reference voltage in a combination and sequence of switching operations defined by a successive approximation search algorithm. Each switching operation in the sequence requires, after the step of switching, a comparison of the voltage input to the comparator with a compare reference voltage after a predetermined settling time from the time the capacitor combination for the switching operation has been switched. The duration of the settling time is controlled for each of the switching operations in the sequence such that at least two of the durations are different.

Abstract: The present invention discloses a transistor array and a layout method, the array including a plurality of first LSB transistors arranged along diagonal directions of a central portion of a first quadrant of an array including a plurality of rows and a plurality of columns; a plurality of first MSB transistors arranged along diagonal directions above and below the plurality of first LSB transistors, respectively; a plurality of second LSB transistors and a plurality of second MSB transistors arranged on a second quadrant of the array to be symmetrical in a Y-axis direction to the plurality of first LSB transistors and the plurality of first MSB transistors; a plurality of third LSB transistors and a plurality of third MSB transistors arranged on a third quadrant of the array to be symmetrical in an X-axis direction to the plurality of first LSB transistors and the plurality of first MSB transistors; and a plurality of fourth LSB transistors and a plurality of fourth MSB transistors arranged on a fourth quadra

Abstract: Open loop common mode driver for switched capacitor input to SAR. A unity gain driver amplifier is disclosed for driving an output node that is connected to a capacitive load. The amplifier includes a first stage amplifier for driving an intermediate node, a positive voltage input node for being connected to an input voltage and a negative input node for receiving a feedback signal. A complimentary output stage is provided having an input connected to the intermediate node and an output connected to the output node, a voltage representative of the voltage on the output node fed back to the negative input of said first stage amplifier. Isolation circuitry then isolates the output node from the negative input node of the first stage amplifier as to phase shift due to large values of the capacitive loading during operation of the driver amplifier.

Abstract: Common centroid layout for parallel resistors in an amplifier with matched AC performance. An amplifier is disclosed that is formed on a silicon substrate that includes first and second differential legs, each driving first and second resistive loads. The first resistive load comprises first and second parallel resistive loads connected on one side thereof to one end of the first differential leg and the other side of each of the first and second parallel resistive loads separately connected to a first reference voltage. The second resistive load comprises third and fourth resistive loads each connected on one side thereof to one end of the second differential leg and the other side of each of the third and fourth parallel resistive loads connected separately to the first reference voltage. Each of the first, second, third and fourth resistive loads is fabricated of a strip of resistive material disposed on the surface of the substrate and having a finite resistivity, length, width and thickness.

Abstract: A transition for transmitting a mm-wave signal from one plane to another, the transition comprising: (a) first and second transmission lines on parallel planes; (b) a third transmission line orthogonal to the first and second transmission lines, wherein either the first and second transmission lines are suitable for transmitting a TEM mode signal and the third transmission line is suitable for transmitting a waveguide mode signal, or the third transmission line is suitable for transmitting a TEM mode signal and the first and second transmission lines are suitable for transmitting a waveguide mode signal; and (c) first and second transducers, the first transducer coupled between the first and third transmission lines, the second transducer coupled between the second and third transmission lines, each of the transducers suitable for converting a TEM mode signal to a waveguide mode signal.

Abstract: Noise cancellation in a single ended SAR converter. A single ended SAR converter front end is disclosed with common mode driver noise cancellation. The SAR converter front end includes a differential amplifier having positive and negative inputs and an output. A switched capacitor array is provided that is operable in a SAR data conversion operation to vary the voltage on one of the positive or negative inputs of the differential amplifier. A common mode driver drives a common mode node with a low impedance common mode voltage signal to a common mode node, and switching circuitry then switches the common mode voltage signal on the common mode node to the positive and negative inputs of the differential amplifier during a portion of a SAR data conversion cycle.

Abstract: A real time data compression method examines whether a present read-in data point is in a predicted tolerable error range. If yes, the previous data point is deemed as redundant and is ignored and after which a new data point is read in for comparing again. When a predetermined amount of data points is continuously ignored, it means the data is steady and only the final data point of these ignored ones is recorded. Otherwise, when data is varied greatly during a period, only the total amount of these varying data points and their value are recorded so the memory capacity for storing the compressed data is saved. Furthermore, the compressed data is stored in a form of a data structure in which the compressed data are expressed by multiple blocks. The block form allows increase of the efficiency of the searching process of the compressed data.

Abstract: As the basic building block of microwave and millimeter wave units and circuits, the microwave switch must fulfill several requirements including low insertion loss, high isolation and small dimensions. For conventional electrostatically actuated microwave MEMS switches, the isolation between DC and RF is achieved using an RF choke. In this invention, a miniature electrostatically actuated microwave switch with a cantilever and employing two resistive lines on a first substrate and act as the actuation electrodes is provided. The resistive lines as the actuation electrodes according to this invention allows one to minimize the switch dimensions, to facilitate the integration and minimize the interference of the propagating microwave or millimeter wave signals.

Abstract: A dither system for a quantizing device, such as a multi-stage pipelined analog-to-digital converter (ADC), derives a dither signal from a clock signal having a sample frequency, the dither signal having a frequency that is one-third of the sample frequency. The dither signal is easily converted to analog and added at the input of the quantizing device to an analog signal to be digitized. A cancellation signal circuit generates a cosine-wave signal from a digital version of the dither signal and programmable coefficients that are a function of amplitude and phase. The cosine-wave signal is combined with the digital output signal from the quantizing device to produce a corrected digital output signal having reduced quantization distortion.

Abstract: A discrete inductive-capacitive (LC) filter selects between at least two inductor banks to tune the LC filter. The filter receives an input signal that includes one or more bands of frequencies. A control signal selects a band of frequencies for processing. A first inductor bank is selected to filter a first band of frequencies, and a second inductor bank is selected to filter a second band of frequencies. A switch circuit couples the input signal to either the first inductor bank or the second inductor bank. The switch circuit selects the first inductor bank if the first band of frequencies is selected, and selects the second inductor bank if the second band of frequencies is selected. The switch circuit electrically isolates the switching of the input signal to the first and the second inductor banks, so as to enhance the Q factor of the LC filter. Circuit and techniques are disclosed to reduce parasitic capacitance in a capacitive bank that employs MOS transistors.

Abstract: Coding section 205 recodes decoded data stored in decoded data storage section 204, data conversion section 206 converts data “0” and “1” output from coding section 205 to “1” and “?1” respectively, sum-of-product calculation section 207 multiplies the data output from data conversion section 206 by the demodulated data (soft decision value) stored in demodulated data storage section 201 and then calculates the sum of the products for 1 TTI and stores the sum-of-product result for each data rate, data rate decision section 208 decides the data rate corresponding to a maximum value of the sum-of-product results as the data rate of the demodulated data. This makes it possible to improve the accuracy of data rate decision and reduce decoding errors of a received signal.

Abstract: A system and method of creating a highly efficient digital amplifier which can take either analog or digital inputs, and produce a high power accurate representation of the input to drive speakers or other low impedance load is described. The system employs a transition detector and delay unit which allows the comparator of the signal modulator to ignore its inputs for a pre-determined number of subsequent clock cycles once an output transition has been detected. Through the use of faster clocks and variable clock cycle skips upon the comparator's output transition, finer resolution of the feedback's clock period for noise-shaping purposes is achieved. Finer resolution of the clock period allows the present invention to employ a more aggressive noise-shaping than previously possible.

Abstract: A circuit for generating a digital data signal from an analog input data signal is disclosed. The circuit comprises a master-slave flip-flop with a clock input for receiving the analog input data signal, an amplitude detecting circuit for detecting the amplitude of the analog input data signal and generating an amplitude detection signal in response thereto, and a phase shifting circuit responsive to the amplitude detection signal for supplying a phase shifted signal to the clock input of the master-slave flip-flop. The circuit may further include a clock recovery circuit for generating a recovered clock signal from a clock signal contained in the analog input data signal. The recovered clock signal may be supplied to the amplitude detecting circuit, or a feedback loop may supply the phase shifted clock signal to the amplitude detecting circuit.

Abstract: The illustrative embodiment of the present invention is a vertical-mode, free-free beam resonator, and micromechanical circuits that include one or more such resonators. In accordance with the illustrative embodiment, the resonator comprises a movable beam that overlies a drive electrode. The movable beam is supported by a plurality of supports, the length of which is substantially less than one-quarter of a wavelength of the resonant frequency of the resonator.

Abstract: A microwave filter including a plurality of resonator cavities (1, 10) arranged in more than two adjacent rows and more than two adjacent columns; wherein each resonator cavity is coupled with at least a sequential adjacent resonator cavity for providing a main path for an electromagnetic energy to be transmitted from a first resonator cavity (1) to a last resonator cavity (10). The electromagnetic energy is injected into the first resonator cavity (1) by an input terminal (20) through an input coupling, and the electromagnetic energy is extracted from the last resonator cavity (10) by an output terminal (21) through an output coupling, and the first (1) and last (10) resonator cavities are non-sequential adjacent cavities.

Abstract: An N-bit word is produced from an M-bit code received on an M-bit line, M being larger than N, the M-bit code comprising at least an M-bit code word and a previous M-bit code word, the M-bit code word comprising different levels at at least two bit positions, and the previous M-bit code word comprising levels opposite to the different levels at the corresponding bit positions, by comparing the levels at the two bit positions of the M-bit code word to obtain a first value, comparing the levels at the two corresponding bit positions of the previous M-bit code word to obtain a second value, detecting that the first value is opposite to the second value, and decoding the M-bit code word responsive to detecting that the first value is opposite to the second value. An advantage of the present invention is that all the lines taking part in the transmission have the same electrical characteristics, the same meaning and the same kind of loads.