Abstract: A test mode circuit of a semiconductor memory device features a test mode controller, a test mode decoder and a test mode item selecting means. The test mode controller outputs a test mode setting signal to control a test mode setting operation in response to a register set signal and address signals which are used in setting a test mode. The test mode decoder, which is controlled by the test mode setting signal, selects a test mode item group in response to upper address bits of the address signal. The particular test mode is then selected from the test mode group in response to lower address bits of the address signal. Accordingly, the number of metal lines used in a test mode circuit can be reduced.

Abstract: A method of providing forward error correction for data services uses a parallel concatenated convolutional code which is a Turbo Code comprising a plurality of eight-state constituent encoders wherein a plurality of data block sizes are used in conjunction with said Turbo Code. A variation uses the method in a cellular radio system. Another variation uses the method in both forward and reverse likes of a cellular radio system.

Abstract: Disclosed is an apparatus for generating an error detection information bit sequence for determining a length of data sequence transmitted in a communication system. The apparatus comprises a plurality of cascaded registers, the number of which is identical to the number of bits in the error detection information bit sequence, and a plurality of adders arranged on paths determined by a predetermined generator polynomial, each of the adders adding a bit sequence received through an input path to a feedback bit sequence. During reception of the control information sequence, an operator generates the feedback bit sequence by sequentially adding bits of the control information sequence to output bits of a final register and provides the generated feedback bit sequence to the adders. After completion of receiving the control information sequence, the operator sequentially adds a preset input bit to output bits of the final register and outputs the addition result as the error detection information bit sequence.

Abstract: A communication isolation system is provided that may employ error correction techniques for the data communicated across an isolation barrier used for connecting electronic circuitry to a communication line. In one embodiment, each data bit to be transmitted to or from the phone line may be transmitted three times across an isolation barrier so that it is possible to withstand a single electronic fast transient event. In another embodiment, the isolation barrier may be a capacitive isolation barrier. In another embodiment, the three transmissions of the data bit may be received across the isolation barrier and delay elements utilized to provide the data bits to a logic circuit in a synchronized fashion so that the three data bits may be compared to determine the error corrected data.

Abstract: A method for providing interactive and iterative testing of integrated circuits including the receiving of a first failing region. The first failing region corresponds to one or more circuits on the integrated circuit. The method generates a set of adaptive algorithmic test patterns for the one or more circuits in response to the first failing region and to a logic model of the integrated circuit. Expected results for the test patterns are determined. The method includes applying the test patterns to the first failing region on the integrated circuit resulting in actual results for the test patterns. The expected results to the actual results are compared. The method also transmits mismatches between the expected results and the actual results to a fault simulator.

Abstract: A semiconductor device having a plurality of memory cells for storing data, an address input circuit having an address signal generation section for independently generating an address signal using a clock signal in a test mode, and a delay circuit for delaying an input time of the address signal from the address input circuit to a subsequent circuit for a predetermined time period which is equal to or longer than the time necessary for the generation of the address signal.

Abstract: A method, computer program product and system for testing stuck-at-faults. A first register may be loaded with a first value where the first value may be written into each entry in a memory array. A second register may be loaded with a second value. A third register may be loaded with either the second value or a third value. The second and third values are pre-selected to test selector circuits for stuck-at-faults with a pattern where the pattern includes a set of bits to be inputted to selector circuits and a set of bits to be stored in the memory cells. A value stored in the n-most significant bits in both the second and third registers may be predecoded to produce a predecode value. The predecode value may be compared with the value stored in the n-most significant bits in an entry in the memory array to determine a stuck-at-fault.

Abstract: The present invention presents a “smart verify” technique whereby multi-state memories are programmed using a verify-results-based dynamic adjustment of the multi-states verify range for sequential-state-based verify implementations. This technique can increase multi-state write speed while maintaining reliable operation within sequentially verified, multi-state memory implementations. It does so by providing “intelligent” element to minimize the number of sequential verify operations for each program/verify/lockout step of the write sequence. In an exemplary embodiment of the write sequence for the multi-state memory during a program/verify cycle sequence of the selected storage elements, at the beginning of the process only the lowest state of the multi-state range to which the selected storage elements are being programmed is checked during the verify phase.

Abstract: An interleaver circuit architectures, which utilizes the relationship between intra-row elements in a matrix, in order to simplify the MOD computations necessary in an interleaver. The interleaver calculates a subset of results, stores those results, performs operations on the stored results in order to obtain new results, then updates at least some of the old results with the new results for the next column operation. The interleaver address is then calculated row by row. By storing only a subset of the results and replacing old results with new results, the interleaver can calculate the interleaver address “on the fly” in one clock cycle with very little delay. The interleaver may also require less power and smaller substrate surface area.

Abstract: A method, apparatus and article of manufacture for decoding concatenated codes includes (in terms of the method): receiving data representing concatenated codes; first inner decoding the received data resulting in first inner message data and parity data; first outer decoding the first inner message data, resulting in reliability information and first outer message data; second inner decoding the first outer message data, resulting in second inner message data; and second outer decoding the second inner message data. The second inner decoding is a function of: the reliability information from the first outer decoding; the first outer message data; and the parity data from the first inner decoding.

Abstract: A method for testing a multi-gigabit transceiver begins by configuring the multi-gigabit transceiver for testing. The processing continues by varying a performance aspect of the multi-gigabit transceiver to produce a varied multi-gigabit transceiver. The processing continues by providing an input test signal to the varied multi-gigabit transceiver. The processing further continues by monitoring an output of the varied multi-gigabit transceiver with respect to the input test signal to determine a level of signal integrity. The processing continues by determining when the level of signal integrity provides a desired performance margin. The processing continues by adjusting a programmable operational setting of the multi-gigabit transceiver when the level of signal integrity does not provide the desired performance margin.

Abstract: Error detection using data block mapping is provided. One method includes receiving a write request to write a user data block having a first block size, generating an error detection code for the user data block, appending the error detection code to the user data block to form an extended data block, and mapping the extended data block to a plurality of actual data blocks, each actual data block having a block size equal to the first block size.

Abstract: A magnetoresistive solid-state storage device (MRAM) employs error correction coding (ECC) to form ECC encoded stored data. In a read operation, parametric values are obtained from storage cells 16 of the device and compared to ranges to establish logical bit values, together with erasure information. The erasure information identifies symbols 206 in a block of ECC encoded data 204 which, from the parametric evaluation, are suspected to be affected by physical failures of the storage cells 16. Where the position of suspected failed symbols 206 is known from this erasure information, the ability of a decoder 22 to perform ECC decoding is substantially enhanced.

Abstract: An electronic device includes a first circuit, a second circuit, and a boundary scan circuit. The boundary scan circuit includes a boundary scan register having a first cell connected to an input node of the first circuit, and a second cell connected between an output node of the first circuit and an input node of the second circuit. The second cell has a latch flip-flop. The boundary scan circuit also includes an interface that enables and disables the latching operation of the latch flip-flop according to an input instruction code. While the latching operation is disabled, the output from the latch flip-flop to the second circuit remains unchanged. In this state, the boundary scan circuit can be used to test the first circuit without unintended effects on the second circuit.

Abstract: A memory-efficient convolutional interleaver/de-interleaver with a memory array, a write commutator, and a read commutator wherein the commutators perform their respective write and read operations relative to a preselected memory cell after a predetermined delay. The delay is chosen using a modulo-based technique, such that an efficient implementation of a Ramsey Type-II interleaver is realized.

Abstract: An optical transmission system allowing precise error rate evaluations is disclosed. A transmitting element performs error-correction coding and transmits an error-correction coded transmission signal. A receiving element decodes the reception signal to produce decoding failure information when a decoding failure occurs, and calculates a number of errors after the error correction decoding based on the decoding failure information. The number of errors is determined based on an error-correcting capability of the error correcting code when the calculated parity information does not perfectly match the extracted parity information.

Abstract: A network processor [200] performs Cyclic Redundancy Check (CRC) operations using specialized hardware circuits [308-308]. The network processor [200] includes a plurality of hardwired CRC polynomials that are used to implement the CRC operations. A CRC instruction selects which polynomial to use when performing the CRC operation.

Abstract: A communication system transmits frames with an arbitrary information length among a plurality of possible information lengths. On receipt of a frame, a receiver performs Viterbi decoding and a CRC operation assuming that the information length of the relavent frame is the same as that of an immediately previous frame. The information length of the frame is detected based on the result of the CRC operation.

Abstract: Briefly, a method and apparatus to generate a quality indicator by measuring an error in coded mode bits of a received frame is provided. The quality indicator may be indicative of modes of a codec.

Abstract: The present invention provides an improved method, an system, and a set of computer implemented instructions for handling a cache containing multiple single-bit hard errors on multiple addresses within a data processing system. Such handles will prevent any down time by logging in the parts to be replaced by an operator when certain level of bit errors is reached. When a hard error exists on a cache address for the first time, serviceable first hard error, that cache line is deleted. Thus the damaged memory device is no longer used by the system. As a result, the system is running with “N?x” lines wherein “N” constitutes the total number of existing lines and “x” is less than “N”. An alternative method is to exchange the damaged memory device to a spare memory device. In order to provide such services, the system must first differentiate whether an error is a soft or hard error.