Abstract: The present invention relates to an organic semiconductor thin film suitably employed in electronics, photonics, bioelectronics, or the like, and a method for forming the same. The present invention further relates to a solution for an organic semiconductor used to form the organic semiconductor thin film and an organic semiconductor device using the organic semiconductor thin film. The transistor of the present invention is manufactured by forming sequentially a gate electrode (2), an insulator layer (3), a source electrode and drain electrode (4, 4) on a glass substrate (5), applying thereto a 0.05% (by mass) solution of pentacene in o-dichlorobenzene and drying the solution to form an organic semiconductor thin film (1). The present invention provides a transistor with superior electronic characteristics because the organic semiconductor thin film (1), which can be formed easily at low cost, is almost free of defects.

Abstract: A metal silicide may be selectively etched by converting the metal silicide to a metal silicate. This may be done using oxidation. The metal silicate may then be removed, for example, by wet etching. A non-destructive low pH wet etchant may be utilized, in some embodiments, with high selectivity by dissolution.

Abstract: Disclosed herein is an organic thin film transistor comprising a substrate, a gate electrode, a gate insulating layer, an organic semiconductor layer, source-drain electrodes and a protective layer wherein a buffer layer is interposed between the organic semiconductor layer and the protective layer. Such a transistor minimizes the deterioration in the performance of the transistor due to ambient air containing oxygen and moisture, and the degeneration in the performance of the transistor caused during mounting a display device.

Abstract: The semiconductor memory cell is characterized in that at least one modulation region is provided between a first gate electrode of the gate electrode configuration and the insulation region, and in that the modulation region has or is formed from a material or modulation material having electrical and/or further material properties that can be modulated in a controllable manner between at least two states in such a way that, in accordance with these states of the modulation material or of the modulation region, the channel region can be influenced electromagnetically, in particular for a given electrical potential difference between the first gate electrode and the source/drain regions.

Abstract: The present invention provides a structure of a semiconductor device that realizes low power consumption even where increased in screen size, and a method for manufacturing the same. The invention forms an insulating layer, forms a buried interconnection (of Cu, Au, Ag, Ni, Cr, Pd, Rh, Sn, Pb or an alloy thereof) in the insulating layer. Furthermore, after planarizing the surface of the insulating layer, a metal protection film (Ti, TiN, Ta, TaN or the like) is formed in an exposed part. By using the buried interconnection in part of various lines (gate line, source line, power supply line, common line and the like) for a light-emitting device or liquid-crystal display device, line resistance is decreased.

Abstract: A semiconductor device in which degradation due to permeation of water and oxygen can be limited, e.g., a light emitting device having an organic light emitting device (OLED) formed on a plastic substrate, and a liquid crystal display using a plastic substrate. A layer to be debonded, containing elements, is formed on a substrate, bonded to a supporting member, and debonded from the substrate. A thin film is thereafter formed on the debonded layer. The debonded layer with the thin film is adhered to a transfer member. Cracks caused in the debonded layer at the time of debonding are thereby repaired. As the thin film in contact with the debonded layer, a film having thermal conductivity, e.g., film of aluminum nitride or aluminum nitroxide is used. This film dissipates heat from the elements and has the effect of preventing deformation and change in quality of the transfer member, e.g., a plastic substrate.

Abstract: A diode-connected lateral transistor on a substrate of a first conductivity type includes a vertical parasitic transistor through which a parasitic substrate leakage current flows. Means for shunting at least a portion of the flow of parasitic substrate leakage current away from the vertical parasitic transistor is provided.

Abstract: The present invention involves a quantum computing apparatus that includes a substrate attached to which is a flux shield upon which is at least one element of circuitry. The flux shield has an aperture. Inside the aperture is a superconducting structure. The superconducting structure and the circuitry interact so that a change in a state of the superconducting structure can be detected by the circuitry. The present invention provides a method for initializing and measuring the state of a superconducting structure by adjusting and measuring the current in an element of circuitry coupled to the structure by a flux shield. The present invention provides a mechanism for coupling qubits. In embodiments of the present invention, qubits are selectively coupled by a coupling circuit that can be on a second substrate. The coupling of the qubit to the coupling circuit is enhanced by the presence of a flux shield.

Abstract: A single evaluation portion is formed by disposing a plurality of MIS transistors used for evaluation having substantially the same structure as that of an actually used MIS transistor. In the evaluation portion, the respective source regions, drain regions, and gate electrodes of the MIS transistors used for evaluation are electrically connected in common to a source pad, a drain pad, and a gate pad, respectively. If the effective gate width of the single evaluation portion exceeds a given value, variations in characteristics evaluated by the evaluation portion approach variations in the characteristics of the entire semiconductor device. The accuracy of evaluating the characteristics of the semiconductor device can thus be improved by using the evaluation portion.

Abstract: Heightening of breakdown voltage of a trench gate type power MISFET is actualized without increasing the number of manufacturing steps. In the manufacturing method of the semiconductor device according to the present invention, p? type semiconductor region and p? type field limiting rings are formed in a gate line area simultaneously in one impurity ion implantation step so as to bring them into contact with a groove having a gate extraction electrode formed therein. Upon formation, supposing that the width of the gate extraction electrode disposed outside the groove is CHSP, and the resistivity of the n? type single crystal silicon layer 1B is ? (?·cm), the CHSP is set to satisfy the following equation: CHSP?3.80+0.148?.

Abstract: An integrated circuit device comprising: a body of a first solid material having an upper surface and a major bottom surface; a pocket of a second solid material having a top surface and a side surface, and a bottom surface which contacts a selected portion of said upper surface on said body; said first and second solid materials being so selected as to form, where said pocket contacts said body at said selected portion of said upper surface, an electronic interfacial barrier which is substantially conductive under an applied bias of at least one selected polarity; and a solid electrically insulating region which meets said barrier and adjoins both said body and at least a line on said side surface of said pocket; wherein at least a part of said solid electrically insulating region comprises nitrogen located at least below the level of said electronic interfacial barrier.

Abstract: A double heterojunction bipolar transistor structure having desirable properties of a low base-emitter turn-on voltage and no electron blocking discontinuities in the base-collector junction. These properties are achieved by selecting base, emitter and collector materials to provide a bandgap profile that exhibits abrupt transitions at the heterojunctions, such that both abrupt transitions are due to transitions in the valence band edge of the bandgap, but not in the conductive band edge of the bandgap.

Abstract: An organic semiconductor device includes an organic semiconductor layer with carrier mobility which is deposited between a pair of electrodes facing each other. At least one of the electrodes includes a carrier relay layer which is in contact with the organic semiconductor layer and has a work function close or equal to an ionized potential of the organic semiconductor layer, and a conductive layer which is formed on the carrier relay layer and has lower resistivity than the carrier relay layer.

Abstract: A CMOS image sensor and a manufacturing method thereof, wherein the gates of several transistors of the CMOS image sensor are formed in an active region defined by an isolation region for a unit pixel of the CMOS image sensor, and a passivation layer composed of insulating layer is formed on the semiconductor substrate. Impurities are ion-implanted into the active region to form one or more diffusion regions of a photo diode of the CMOS image sensor, wherein the passivation layer prevents a boundary portion of the active region from being ion-implanted. Thus, damages by ion implantation at the boundary portion between the diffusion region for the photo diode and the isolation region are prevented, and the dark current of the CMOS image sensor is reduced.

Abstract: A bi-directional EOS/ESD protection device, suitable for application on an I/O port. The circuit includes a P-type semiconductor layer, a first N-type conductive layer, a second N-type conductive layer, a first P-type doped region, a first N-type doped region, a second N-type doped region and a second P-type doped region. The first N-type conductive layer and the second N-type conductive layer are formed separately on the P-type semiconductor layer. The first P-type doped region and the first N-type doped region are formed on the first N-type conductive layer. The second N-type doped region and the second P-type doped region are formed on the second N-type conductive layer. The first N-type conductive layer is coupled to an I/O pad, and the second N-type conductive layer is coupled to a power line. Signals irrespective of conductivity type are transmitted via the I/O pad.

Abstract: A substrate includes a substrate body, a first thin film pattern, a second thin film pattern and a third thin film pattern. The substrate body includes a first surface and a second surface that is opposite to the first surface. The first, second and third thin film patterns are formed on the first surface of the substrate body. The first, second and third thin film patterns include first, second and third liquid crystal of which first, second and third liquid crystal molecules are arranged in first direction in order to transmit only first, second and third lights having first, second and third wavelength and a specific polarizing axis, respectively. Therefore, parts of a substrate for a display apparatus may be reduced, so that a process of manufacturing the substrate may be simplified.

Abstract: A method of fabricating a tunable quantum dot apparatus, comprising: forming multi-quantum wells sandwiched substantially between at least two barrier layers; spin coating a non-continuous mask onto at least one of said barrier layers; forming a gate material onto the mask, wherein the non-continuity of the mask substantially prevents formation of a continuous gate material layer; lifting off at least a portion of the gate material; self isolating the gate material; and, forming a top contact onto at least a portion of said barrier layers

Abstract: Semiconductor devices employing siloxane epoxy polymers as low-? dielectric films are disclosed. The devices include a semiconductor substrate, one or more metal layers or structures and one or more dielectric films, wherein at least one dielectric film in the devices is a siloxane epoxy polymer. Use of siloxane epoxy polymers is advantageous, in part, because the polymers adhere well to metals and have dielectric constants as low as 1.8. Thus, the disclosed semiconductor devices offer much better performance than devices fabricated using conventional dielectric materials. Furthermore, the siloxane epoxy polymer dielectrics are fully curable at low temperatures, exhibit low leakage currents, and remain stable at temperatures greater than 400° C.

Abstract: Impurities for threshold voltage adjustment are implanted using a resist film and a protective dielectric as implantation masks from directions inclined at 10° through 30° with respect to the direction vertical to the principal surface of a semiconductor substrate 1 when viewed in cross section taken along the gate width direction. Thus, first low-concentration impurity implantation regions are formed to overlap each other in the central part of an active region for a memory cell MIS transistor Mtrs of an SRAM. Furthermore, after an isolation is formed, a second low-concentration impurity implantation region is formed in an active region for each of MIS transistors Ltr, Mtrs and Mtrl by implanting impurity ions without using implantation masks. The MIS transistors Ltr, Mtrs and Mtrl formed after the completion of the fabricating process have substantially the same threshold voltage.

Abstract: It is an object to provide techniques for forming a field emission device of a field emission display device with the use of an inexpensive large-sized substrate according to the process that enables improving productivity. A field emission device according to the present invention includes a cathode electrode formed on an insulating surface of a substrate and a convex electron emission portion formed at a surface of the cathode electrode, and the cathode electrode and the electron emission portion include the same semiconductor film. The electron emission portion has a conical shape or a whiskers shape.

Abstract: A small metal member (50) is secured to a surface (32) of a plastic member (30) by lock tabs (54) bent into a recess (34) in the surface (32), and the plastic material of a central boss (38) in the recess (34) is bulk deformed over ends (68) of the lock tabs (54) forming a recessed joint (70).