Abstract: A wireless communication device that includes a first electrode connected to a first terminal electrode of an RFIC element and a second electrode connected to a second terminal electrode of the RFIC element. Moreover, the first electrode has a longitudinal direction and a lateral direction and has a first portion connected to the first terminal electrode and a second portion that faces the first portion and the second electrode. The first portion has an extended portion that extends in the longitudinal direction beyond a connection point between the second electrode and the second terminal electrode.

Abstract: A quantum computing device is fabricated by forming, on a superconductor layer, a first resist pattern defining a device region and a sensing region within the device region. The superconductor layer within the sensing region is removed, exposing a region of an underlying semiconductor layer outside the device region. The exposed region of the semiconductor layer is implanted, forming an isolation region surrounding the device region. Using an etching process subsequent to the implanting, the sensing region and a portion of the device region of the superconductor layer adjacent to the isolation region are exposed. By depositing a first metal layer within the sensing region, a tunnel junction gate is formed. A sensing region gate is formed by coupling the semiconductor layer with a second metal layer. A nanorod contact using the second metal within the portion of the device region outside the sensing region is formed.

Abstract: A quantum computing device is fabricated by forming, on a superconductor layer, a first resist pattern defining a device region and a sensing region within the device region. The superconductor layer within the sensing region is removed, exposing a region of a first surface of an underlying semiconductor layer outside the device region. The exposed region of the semiconductor layer is implanted, forming an isolation region surrounding the device region. The sensing region and a portion of the device region of the superconductor layer are exposed. A sensing region contact is formed by coupling the first surface of the semiconductor layer with a first metal layer. A nanorod contact using the first metal within the portion of the device region outside the sensing region is formed. By depositing a second metal layer on a second surface of the semiconductor layer within the sensing region, a tunnel junction gate is formed.

Abstract: The various embodiments described herein include methods, devices, and circuits for reducing or minimizing current crowding effects in manufactured superconductors. In some embodiments, a superconducting circuit includes: (1) a first component having a first connection point, the first connection point having a first width; (2) a second component having a second connection point, the second connection point having a second width that is larger than the first width; and (3) a connector electrically connecting the first connection point and the second connection point, the connector including: (a) a first taper having a first slope and a non-linear shape; (b) a second taper having a second slope; and (c) a connecting portion connecting the first taper to the second taper, the connecting portion having a third slope that is less than the first slope and less than the second slope.

Abstract: Embodiments of semiconductor structures including word line contact structures for three-dimensional memory devices and fabrication methods for forming word line contact structures are disclosed. The semiconductor structures include a staircase structure having a plurality of steps, and each step includes a conductive layer disposed over a dielectric layer. The semiconductor structures further include a barrier layer disposed over a portion of the conductive layer of each step. The semiconductor structures also include an etch-stop layer disposed on the barrier layer and an insulating layer disposed on the etch-stop layer. The semiconductor structures also include a plurality of conductive structures formed in the insulating layer and each conductive structure is formed on the conductive layer of each step.

Abstract: There is provided a technique that includes forming a film containing silicon, oxygen, carbon, and nitrogen on a substrate by performing a cycle a predetermined number of times, the cycle including: forming a first layer containing silicon, carbon, and nitrogen by performing a set a predetermined number of times, the set including: supplying a first precursor, which contains at least two Si—N bonds and at least one Si—C bond in one molecule, to the substrate; and supplying a second precursor, which contains nitrogen and hydrogen, to the substrate; and forming a second layer by supplying an oxidant to the substrate, to thereby oxidize the first layer.

Abstract: An interposer includes: a base substrate; an interconnection structure on a top surface of the base substrate and including a metal interconnection pattern; an upper passivation layer on the interconnection structure and having compressive stress; a lower passivation layer under a bottom surface of base substrate, the lower passivation layer having compressive stress that is less than the compressive stress of the upper passivation layer; a lower conductive layer under the lower passivation layer; and a through electrode penetrating the base substrate and the lower passivation layer. The through electrode electrically connects the lower conductive layer to the metal interconnection pattern of the interconnection structure.

Abstract: A method for joining a microelectronic chip to at least one wire element comprises a first step of applying a cover to a first face of the microelectronic chip, the cover being configured to form, with the first face, at least one temporary side groove. The method additionally comprises a step of inserting the wire element into the temporary groove. The method further comprises a step of attaching the wire element to the microelectronic chip. The method additionally comprises a step of removing the cover from the microelectronic chip.

Abstract: A method for manufacturing an electrolytic capacitor includes a first step, a second step, and a third step. In the first step, a capacitor element is formed. The capacitor element includes an anode body, a cathode body, and a separator. The anode body includes a dielectric layer formed on a surface of the anode body. And the separator is disposed between the anode body and the cathode body. In the second step, the capacitor element is impregnated with a treatment solution containing an acid component and a base component. In the third step, the capacitor element is, after the second step, impregnated with a conductive polymer dispersion in a state that a part of the treatment solution remains in the capacitor element. The conductive polymer dispersion is obtained by dispersing, in a solvent, conductive polymer particles each including polyanion. A pH of the treatment solution is higher than a pH of the conductive polymer dispersion.

Abstract: An asymmetrically shaped chip-scale packaging (CSP) light-emitting device (LED) includes an LED chip, a photoluminescent structure (or a light-transmitting structure), and a reflective structure. The photoluminescent structure covers the upper surface and/or the edge surface of the LED chip; and the reflective structure at least partially covers the edge surface of the photoluminescent structure. The reflective structure partially reflects the primary light emitted from the edge surface of the LED chip or the converted secondary light radiated from the edge surface of the photoluminescent structure, therefore shaping the radiation pattern asymmetrically.

Abstract: A method for making a semiconductor device may include forming an isolation region adjacent an active region in a semiconductor substrate, and selectively etching the active region so that an upper surface of the active region is below an adjacent surface of the isolation region and defining a stepped edge therewith. The method may further include forming a superlattice overlying the active region. The superlattice may include stacked groups of layers, with each group of layers comprising stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions.

Abstract: Microfeature workpieces having alloyed conductive structures, and associated methods are disclosed. A method in accordance with one embodiment includes applying a volume of material to a bond pad of a microfeature workpiece, with the volume of material including a first metallic constituent and the bond pad including a second constituent. The method can further include elevating a temperature of the volume of material while the volume of material is applied to the bond pad to alloy the first metallic constituent and the second metallic constituent so that the first metallic constituent is alloyed generally throughout the volume of material. A thickness of the bond pad can be reduced from an initial thickness T1 to a reduced thickness T2.

Abstract: Amorphous multi-component metallic films can be used to improve the performance of electronic devices such as resistors, diodes, and thin film transistors. An amorphous hot electron transistor (HET) having co-planar emitter and base electrodes provides electrical properties and performance advantages over existing vertical HET structures. Emitter and the base terminals of the transistor are both formed in an upper crystalline metal layer of an amorphous nonlinear resistor. The emitter and the base are adjacent to one another and spaced apart by a gap. The presence of the gap results in two-way Fowler-Nordheim tunneling between the crystalline metal layer and the amorphous metal layer, and symmetric I-V performance. Meanwhile, forming the emitter and base terminals in the same layer simplifies the HET fabrication process by reducing the number of patterning steps.

Abstract: Various embodiments of the present disclosure are directed towards an integrated circuit (IC) including a pillar structure abutting a trench capacitor. A substrate has sidewalls that define a trench. The trench extends into a front-side surface of the substrate. The trench capacitor includes a plurality of capacitor electrode layers and a plurality of capacitor dielectric layers that respectively line the trench and define a cavity within the substrate. The pillar structure is disposed within the substrate. The pillar structure has a first width and a second width less than the first width. The first width is aligned with the front-side surface of the substrate and the second width is aligned with a first point disposed beneath the front-side surface.

Abstract: A capacitor comprising a solid electrolytic capacitor element that contains a sintered porous anode body, a dielectric that overlies the anode body, and a solid electrolyte is provided. The solid electrolyte contains an interior conductive polymer layer overlying the dielectric, an adhesive film that overlies the interior conductive polymer layer, which may be formed by sequential vapor deposition. An exterior conductive polymer layer also overlies the adhesive film.

Abstract: Josephson magnetic memory cells with a semiconductor-based magnetic spin valve are described. An example memory cell includes a first superconducting electrode, a second superconducting electrode, and a semiconductor-based magnetic spin valve arranged between the two superconducting electrodes. The semiconductor-based magnetic spin valve includes a semiconductor layer and a first ferromagnetic insulator arranged near the semiconductor layer, arranged on a first side of the semiconductor layer, configured to provide a fixed magnetization oriented in a first direction.

Abstract: A method for manufacturing a gas sensor may be provided, the method comprising the steps of: preparing a porous base substrate; providing, on the porous base substarte, a source solution having graphene dispersed in a base solvent; manufacturing a graphene-impregnated base substrate by means of a driving process; and forming a first electrode and a second electrode on the graphene-impregnated base substrate.

Abstract: A capacitor comprising a solid electrolytic capacitor element that contains a sintered porous anode body, a dielectric that overlies the anode body, and a solid electrolyte that overlies the dielectric. The capacitor further contains a barrier film that is formed by vapor deposition and that is positioned between the dielectric and the solid electrolyte or overlies the dielectric.

Abstract: This disclosure provides an array substrate, a method for fabricating the same, a display panel, and a display device, where a first photo-resist layer is stripped in a changed order in that the first photo-resist layer on a source-drain is stripped through wet etching before a ohm contact layer film and an active layer film are etched in an electrically-conductive channel area (i.e., an electrically-conductive channel of a TFT is etched) to form an ohm contact layer and an active layer.

Abstract: When a film thickness of a second epitaxial film is measured, an infrared light is irradiated from a surface side of the second epitaxial film onto a base layer on which a first epitaxial film and the second epitaxial film are formed. A reflected light from an interface between the first epitaxial film and the base layer and a reflected light from a surface of the second epitaxial film are measured to obtain a two-layer film thickness, which is a total film thickness of the first epitaxial film and the second epitaxial film. The film thickness of the second epitaxial film is calculated by subtracting a one-layer film thickness, which is a film thickness of the first epitaxial film, from the two-layer film thickness.