Abstract: A Si substrate is etched through a first mask material layer formed on the Si substrate and serving as a mask, to form a Si pillar on a Si substrate. Subsequently, a second mask material layer formed so as to surround the side surface of the Si pillar is used as a mask to form a Si-pillar base part surrounding the Si pillar. Subsequently, the first and second mask material layers are used as masks to form a SiO2 layer so as to occupy the whole section of the Si-pillar base part and connect to the Si substrate positioned in a region around the Si-pillar base part. Recessed portions are formed in the upper and lower regions of the SiO2 layer. Subsequently, on the SiO2 layer, an SGT is formed so as to include a gate insulating HfO2 layer surrounding the Si pillar, a gate conductor TiN layer, N+ layers serving as the source or drain within the Si pillar, and a Si pillar serving as the channel between the N+ layers.

Abstract: A method of forming a three-dimensional transistor device. The method may include providing a fin array on a substrate, the fin array comprising a plurality of fin structures, formed from a monocrystalline semiconductor, and disposed subjacent to a hard mask layer. The method may include directing angled ions at the fin array, wherein the angled ions form a non-zero angle of incidence with respect to a perpendicular to a plane of the substrate. The angled ions may etch the plurality of fin structures to form a stack of isolated nanowires, within a given fin structure.

Abstract: A circuit module includes a flat substrate, a frame substrate, a first electronic component, and a first sealing member. First connection electrodes are disposed at a peripheral portion of one main surface of the flat substrate. Second connection electrodes are disposed on one main surface of the frame substrate at locations corresponding to the first connection electrodes. Each of the first connection electrodes and a corresponding one of the second connection electrodes are connected to each other via a first connection member. The first electronic component is sealed by the first sealing member. The first electronic component and the first sealing member are disposed in a cavity defined by the one main surface of the flat substrate and an inner surface of the frame substrate. The first sealing member is separated from the inner surface of the frame substrate.

Abstract: A semiconductor module includes a substrate, a semiconductor element, and a wire. The semiconductor element is joined onto the substrate and has a surface electrode. Both ends of the wire are bonded to the substrate such that the wire passes over the surface electrode of the semiconductor element. The wire is electrically connected to the surface electrode.

Abstract: A method for producing an electrode for an aluminum electrolytic capacitor is provided that can reduce defects in a chemical formation film formed at a chemical formation voltage of 500 V or higher. For producing the electrode for an aluminum electrolytic capacitor, an aluminum electrode is brought into contact with pure water having a temperature of 70° C. or higher to form a hydrated film having a suitable film thickness on the aluminum electrode at a hydration step, and then chemical formation is performed thereon at a chemical formation voltage of 500 V or higher in a chemical formation solution having a temperature of 40° C. or higher at a chemical formation step. At the chemical formation step, when the relative velocity of the chemical formation solution to the aluminum electrode is represented by a three-dimensional velocity vector B?A and the absolute value of the velocity vector B?A is represented by |B?A|, the absolute value |B?A| of the velocity vector satisfies the following conditional formula.

Abstract: This invention relates to integrating pixelated micro-devices into a system substrate. Defined are methods of transferring a plurality of micro-devices into a receiver substrate where a plurality of micro-devices is arranged in one or more cartridges that are aligned and bonded to a template. Further, defining the transfer process, the micro-devices may be selected, identified as defective and a transfer adjustment made based on defective micro-devices.

Abstract: A display device is provided. The display device includes a display panel including first and second display substrates that face each other, having an overlap area in which the first and second display substrates overlap with each other, and having a protruding area on one side of the overlap area, a sealing member between the first and second display substrates along edges of the overlap area, and at least one chamfered portion including a first chamfered portion, which is formed on at least one side of the protruding area, and a second chamfered portion, which is formed on the overlap area and adjacent to the first chamfered portion, wherein in the second chamfered portion, an end of the first display substrate is positioned beyond an end of the second display substrate.

Abstract: Embodiments of the invention are directed to a method of fabricating a field effect transistor device, wherein the fabrication operations include forming a channel region over a substrate, forming a gate region over a top surface and along sidewalls of the channel region, and forming a source or drain (S/D) region over the substrate. A bottom encapsulated air-gap is formed over the substrate, and a first portion of the bottom encapsulated air-gap is positioned between the gate region and the S/D region. The first portion of the bottom encapsulated air-gap is further positioned below the top surface of the channel region.

Abstract: A foldable, flexible display apparatus includes a flexible display panel which displays an image and includes a display side on which the image is displayed and of which portions thereof face each other in a folded state of the flexible display apparatus; a cover window on the display side of the flexible display panel and including: a window film comprising a transparent plastic film having a modulus of elasticity of about 6.3 gigapascals or more; and a coating layer on the window film, and configured to be transparent and to protect the window film from physical damage thereto; and an adhesive layer between the window film and the display side of the flexible display panel, and configured to have elasticity and bond the window film and the flexible display panel to each other.

Abstract: A tap cell configured to enable electrical connection from a buried power rail of an integrated circuit to a power distribution network includes. The tap cell includes a buried power rail layer including VDD and VSS power supply lines, insulating layers and metal layers alternately arranged on the buried power rail layer, a first power supply interconnect in metal layer M1 or higher electrically coupled to the VDD power supply line, and a second power supply interconnect in metal layer M1 or higher electrically connected to the VSS power supply line. The first power supply interconnect and the second power supply interconnect are configured to be electrically connected to the power distribution network, and the VDD and VSS power supply lines are configured to supply power from the power distribution network to the buried power rail of the integrated circuit. The tap cell is free of any active semiconductor devices.

Abstract: A display device includes a substrate that includes a display area and a peripheral area, a transistor in the display area, a pixel electrode connected to the transistor, a common electrode that overlaps the pixel electrode, and an organic insulation layer that is between the common electrode and the substrate, and overlaps at least a part of the peripheral area, wherein a thickness of a portion of the organic insulation layer overlapping the display area, and a thickness of a portion of the organic insulation layer overlapping the peripheral area, are different from each other, and the organic insulation layer includes a valley that penetrates the organic insulation layer, while overlapping the peripheral area.

Abstract: Embodiments are directed to a Radio Frequency Identification (RFID) integrated circuit (IC) having a first circuit block electrically coupled to first and second antenna contacts. The first antenna contact is disposed on a first surface of the IC and the second antenna contact is disposed on a second surface of the IC different from the first surface. A substrate of the RFID IC, or a portion of the IC substrate, electrically couples the first circuit block to at least one of the first and second antenna contacts. The IC includes one or more interfaces or barrier regions that at least partially electrically isolate the first circuit block from the rest of the IC substrate.

Abstract: The method is provided for fabricating an optical metasurface. The method may include depositing a conductive layer over a holographic region of a wafer and depositing a dielectric layer over the conducting layer. The method may also include patterning a hard mask on the dielectric layer. The method may further include etching the dielectric layer to form a plurality of dielectric pillars with a plurality of nano-scale gaps between the pillars.

Abstract: The present disclosure relates to a semiconductor device and an electronic apparatus that make it possible to provide a higher voltage resistance. An outer-peripheral structure region is provided in an n-type well on a surface of a semiconductor substrate, the outer-peripheral structure region being arranged to surround an outer periphery of a region in which a plurality of semiconductor elements is formed. Further, an anode is arranged in an innermost in the outer-peripheral structure region, and a plurality of guard rings is multiply arranged on an outside of the anode. Furthermore, a field plate covering the anode and a field plate covering a guard ring adjacent to the anode are formed to be electrically connected to each other so as to be combined. The present technology is applicable to, for example, various semiconductor devices.

Abstract: The present disclosure provides an LED package structure, a carrier, and a method for manufacturing a carrier. The carrier includes a substrate and an electrode layer disposed on the substrate. The electrode layer includes at least one bonding portion that has a plurality of elongated microstructures recessed in a surface thereof.

Abstract: An imaging device includes: a photoelectric converter which converts light into signal charges; a charge accumulation region which is electrically connected to the photoelectric converter, and accumulates the signal charges; a transistor having a gate electrode which is electrically connected to the charge accumulation region; and a contact plug which electrically connects the photoelectric converter to the charge accumulation region, is in direct contact with the charge accumulation region, and comprises a semiconductor material.

Abstract: A high volumetric energy and power density supercapacitor is provided. This supercapacitor includes a coin cell, a spring lamination, a working electrode, a counter electrode, a separator, and an ionic liquid electrolyte. The working and counter electrodes are N—P doping porous graphene coated on Al substrate. The ionic liquid electrolyte is EMI-FSI. The method of producing N—P doping porous graphene includes following steps: S1: Graphite oxide is quickly transferred into the furnace, which had been held at 300° C. and the porous graphene can be produced. S2: The porous graphene and red phosphorus are put together in the evacuated tube furnace and heated to 700° C. for 1 hr. S3: Heated to 800° C. for 30 min in a mixed argon and ammoniac atmosphere and then the N—P doping porous graphene can be made. The capacitance of the supercapacitor is 105 F/g and the volumetric power density is 1.19 kW/L.

Abstract: A method for producing an electrical component via a 3D printing includes preparing a first layer which includes a valve metal powder, consolidating at least a portion of the valve metal powder of the first layer via a first selective irradiation with a laser, applying a second layer which includes the valve metal powder to the first layer, consolidating at least a portion of the valve metal powder of the second layer via a second selective irradiation with the laser so as to form a composite of the first layer and of the second layer, applying respective additional layers which include the valve metal powder to the composite, and consolidating at least a portion of the valve metal powder of the respective additional layers via a respective additional selective irradiation with the laser to thereby obtain the electrical component.

Abstract: A method for forming active regions of a semiconductor device comprising forming a nanosheet stack on a substrate, forming the nanosheet stack comprising forming a sacrificial nanosheet layer on the substrate, and forming a nanosheet layer on the sacrificial nanosheet layer, forming an etch stop layer on the nanosheet stack, forming a mandrel layer on the etch stop layer, removing portions of the mandrel layer to form a mandrel on the etch stop layer, forming sidewalls adjacent to sidewalls of the mandrel, depositing a fill layer on exposed portions of the etch stop layer, removing the sidewalls and removing exposed portions of the etch stop layer and the nanosheet stack to expose portions of the substrate.

Abstract: A method of forming a gate structure of a semiconductor device including depositing a high-k dielectric layer over a substrate is provided. A dummy metal layer is formed over the high-k dielectric layer. The dummy metal layer includes fluorine. A high temperature process is performed to drive the fluorine from the dummy metal layer into the high-k dielectric layer thereby forming a passivated high-k dielectric layer. Thereafter, the dummy metal layer is removed. At least one work function layer over the passivated high-k dielectric layer is formed. A fill metal layer is formed over the at least one work function layer.