Abstract: A bonding apparatus and method includes: a stage configured to fix a first electric component; a pressing unit configured to press a conductive adhesive film and a second electric component onto the first electric component; a driver configured to control movement of the pressing unit along a direction; and a plurality of sensors at different positions on the stage and configured to sense a change in capacitance with the pressing unit, wherein the pressing unit includes a flat metal material in first regions facing the plurality of sensors.

Abstract: A semiconductor structure is provided that includes nanosheet containing devices having a bottom dielectric isolation structure and high quality source/drain (S/D) structures. In the present application, the bottom dielectric isolation structure is formed after the S/D structures to ensure high quality epitaxy for both long channel and short channel nanosheet containing devices. The bottom dielectric isolation structure of the present application has a first portion that is located beneath each nanosheet stack and a second portion that is located in a single diffusion break point trench.

Abstract: A semiconductor device may include active patterns extended in a first direction and spaced apart from each other in the first direction, a device isolation layer defining the active patterns, an insulating structure provided between the active patterns and between the device isolation layer, and a gate structure disposed on the insulating structure and extended in a second direction crossing the first direction. The gate structure may include an upper portion and a lower portion. The lower portion of the gate structure may be enclosed by the insulating structure.

Abstract: In some examples, an electronic device comprises a first component having a surface, a second component having a surface, and a bond layer positioned between the surfaces of the first and second components to couple the first and second components to each other. The bond layer includes a set of metallic nanowires and a dielectric portion. The dielectric portion comprises a polymer matrix and dielectric nanoparticles.

Abstract: A capacitor comprising a solid electrolytic capacitor element that contains a sintered porous anode body, a dielectric film that is formed by sequential vapor deposition and overlies the anode body, and a solid electrolyte that overlies the dielectric film is provided. A method for forming a solid electrolytic capacitor element is also provided.

Abstract: A mesa structure includes a substrate. A mesa protrudes out of the substrate. The mesa includes a slope and a top surface. The slope surrounds the top surface. A lattice damage area is disposed at inner side of the slope. The mesa can optionally further includes an insulating layer covering the lattice damage area. The insulating layer includes an oxide layer or a nitride layer.

Abstract: A semiconductor device includes a first cell and a second cell. The first cell includes a first circuit, and the first circuit includes a first gate. The second cell is disposed adjacent the first cell and includes a second circuit which includes a second gate. The doping concentration of the first circuit is different from that of the second circuit, and the first gate and the second gate have the same gate critical dimension. A method for manufacturing the semiconductor device is also disclosed herein.

Abstract: The present disclosure provides a semiconductor structure and a method for manufacturing a semiconductor structure. The semiconductor structure includes a substrate, a transistor on the substrate, and an isolation structure. The transistor includes an epitaxial region on the substrate, having a first side boundary and a second side boundary opposite to the first side boundary, wherein the first side boundary of the epitaxial region is conformal to a sidewall of the isolation structure.

Abstract: Provided are a method for manufacturing a thin-film transistor (TFT) substrate and a TFT substrate. The method for manufacturing a TFT substrate is capable of effectively protecting the surface of the inorganic insulating layer in the mark area and the mark peripheral area during performing dry etching on the metal layer by providing a protective layer between the inorganic insulating layer and the metal layer to reduce the surface damage of the inorganic insulating layer during dry etching, thereby effectively improving the recognition rate of the alignment mark by the CCD camera in the subsequent alignment process, improving the alignment detection accuracy, and avoiding subsequent alignment anomalies. In addition, it is not necessary to adjust the dry etching parameters of the metal layer, which indirectly reduces the process constraints of the dry etching process, avoids modification and calibration of the alignment CCD camera, and lowers production costs.

Abstract: A pixel cell includes an electrically conductive tunnel contact formed across a surface of a source follower gate, the tunnel contact having a first end, a second end, and an intermediate portion between the first and second ends. The first end is coupled to a floating diffusion FD, the second end is coupled to the first doped region of a reset transistor RST. The tunnel contact is formed in physical and in electrical contact with the surface of the source follower gate for a length of the intermediate portion substantially equal to a width of the source follower gate. Methods of forming the pixel cell are also described.

Abstract: A semiconductor structure is disclosed. The semiconductor structure includes a staircase structure disposed over a substrate. The staircase structure includes a plurality of layer stacks, where each layer stack is made of a first material layer over a portion of a second material layer. The staircase structure further includes a plurality of landing pads, where each landing pad is disposed over another portion of the second material layer of a respective layer stack.

Abstract: A method of forming a GaN film includes following steps. A silicon-on-insulator (SOI) substrate is provided. The SOI substrate includes a substrate, an insulator layer and a silicon layer. The insulator layer is disposed on the substrate and the silicon layer is disposed on the insulator layer. The silicon layer is pattered into a patterned silicon layer including a plurality of recessed features. Each recessed feature has a sidewall. A plurality of GaN structures are epitaxially grown from the sidewalls, and the GaN structures are separated from each other. The GaN structures are continuously epitaxially grown vertically and horizontally to merge the GaN structures over top of the patterned silicon layer to form a GaN layer.

Abstract: Disclosed herein is a method of forming an electrical connecting structure having nano-twins copper. The method includes the steps of (i) forming a first nano-twins copper layer including a plurality of nano-twins copper grains; (ii) forming a second nano-twins copper layer including a plurality of nano-twins copper grains; and (iii) joining a surface of the first nano-twins copper layer with a surface of the second nano-twins copper layer, such that at least a portion of the first nano-twins copper grains grow into the second nano-twins copper layer, or at least a portion of the second nano-twins copper grains grow into the first nano-twins copper layer. An electrical connecting structure having nano-twins copper is provided as well.

Abstract: The present disclosure relates to a solid-state imaging element, a manufacturing method, and an electronic apparatus, in which irregular reflection of light inside a solid-state imaging element package can be suppressed. In the solid-state imaging element, a plurality of pixels is planarly arranged, a connection portion utilized for connection to the outside is provided on a more outer side than an imaging region, and an open portion that is opened up to the connection portion from a light incident surface side of the imaging region where light is incident is formed. Additionally, a plurality of protruding portions periodically arranged is formed on a counterbore surface that is a surface inside the open portion excluding the connection portion. The present technology can be applied to, for example, a back-illuminated type or layered CMOS image sensor.

Abstract: A capacitor comprising a solid electrolytic capacitor element that a sintered porous anode body, a dielectric that overlies the anode body, and a solid electrolyte is provided. The solid electrolyte contains an interior conductive polymer film that overlies the dielectric, which may be formed by sequential vapor deposition. An exterior conductive polymer layer also overlies the interior conductive polymer film.

Abstract: In one embodiment, a semiconductor device includes a first substrate including first and second regions on its surface, a first control circuit on the first substrate in the first region, a first memory cell array above the first control circuit in the first region and connected to the first control circuit, and a first pad above the first memory cell array in the first region and connected to the first control circuit. The device further includes a second control circuit on the first substrate in the second region, a second memory cell array above the second control circuit in the second region and connected to the second control circuit, a second pad above the second memory cell array in the second region and connected to the second control circuit, and a connection line above the first and second memory cell arrays and connecting the first and second pads.

Abstract: A semiconductor on insulator type structure, which may be used for a front side type imager, successively comprises, from its rear side to its front side, a semiconductor support substrate, an electrically insulating layer and an active layer comprising a monocrystalline semiconductor material. The active layer is made of a semiconductor material having a state of mechanical stress with respect to the support substrate, and the support substrate comprises, on its rear side, a silicon oxide layer, the thickness of the oxide layer being chosen to compensate bow induced by the mechanical stress between the active layer and the support substrate during cooling of the structure after the formation by epitaxy of at least a part of the active layer on the support substrate.

Abstract: A number of monolithic diode limiter semiconductor structures are described. The diode limiters can include a hybrid arrangement of diodes with different intrinsic regions, all formed over the same semiconductor substrate. In one example, two PIN diodes in a diode limiter semiconductor structure have different intrinsic region thicknesses. The first PIN diode has a thinner intrinsic region, and the second PIN diode has a thicker intrinsic region. This configuration allows for both the thin intrinsic region PIN diode and the thick intrinsic region PIN diode to be individually optimized. The thin intrinsic region PIN diode can be optimized for low level turn on and flat leakage, and the thick intrinsic region PIN diode can be optimized for low capacitance, good isolation, and high incident power levels. This configuration is not limited to two stage solutions, as additional stages can be used for higher incident power handling.

Abstract: A thin film transistor and a manufacture method thereof, an array substrate and a manufacture method thereof are provided. The manufacture method of the thin film transistor includes: providing a base substrate; and forming a gate electrode, a first electrode, a second electrode and a semiconductor layer of the thin film transistor on the base substrate. At least one of the gate electrode, the first electrode and the second electrode includes N portions that are stacked in a direction perpendicular to the base substrate, adjacent two of the N portions are in direct contact with each other, and N is a positive integer more than or equal to 2. The method includes: performing N patterning processes to respectively form the N portions.

Abstract: A wireless communication device that includes a first electrode connected to a first terminal electrode of an RFIC element and a second electrode connected to a second terminal electrode of the RFIC element. Moreover, the first electrode has a longitudinal direction and a lateral direction and has a first portion connected to the first terminal electrode and a second portion that faces the first portion and the second electrode. The first portion has an extended portion that extends in the longitudinal direction beyond a connection point between the second electrode and the second terminal electrode.